2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <arch/romcc_io.h>
24 #include <device/pci_ids.h>
27 static void i82371eb_enable_rom(void)
33 * Note: The Intel 82371AB/EB/MB ISA device can be on different
34 * PCI bus:device.function locations on different boards.
35 * Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
36 * But scanning for the PCI IDs (instead of hardcoding
37 * bus/device/function numbers) works on all boards.
39 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
40 PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
42 /* Enable access to the whole ROM, disable ROM write access. */
43 reg16 = pci_read_config16(dev, XBCS);
44 reg16 |= LOWER_BIOS_ENABLE;
45 reg16 |= EXT_BIOS_ENABLE;
46 reg16 |= EXT_BIOS_ENABLE_1MB;
47 reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
48 pci_write_config16(dev, XBCS, reg16);