src/southbridge/intel/i3100/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Arastra, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  *
  19  */
  20
  21 /* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */
  22
  23 #include <console/console.h>
  24 #include <device/device.h>
  25 #include <device/pci.h>
  26 #include <device/pci_ids.h>
  27 #include <device/pci_ops.h>
  28 #include "i3100.h"
  29
  30 typedef struct southbridge_intel_i3100_config config_t;
  31
  32 static void sata_init(struct device *dev)
  33 {
  34         u8 ahci;
  35         u32 *ahci_bar;
  36         config_t *config = dev->chip_info;
  37
  38         if (config == NULL) {
  39            printk(BIOS_ERR, "i3100_sata: error: device not in devicetree.cb!\n");
  40            return;
  41         }
  42
  43         /* Get the chip configuration */
  44         ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
  45
  46         /* Enable SATA devices */
  47         printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
  48
  49         if(ahci) {
  50           /* AHCI mode */
  51           pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
  52
  53           /* Enable ports */
  54           pci_write_config8(dev, SATA_PCS, 0x03);
  55           pci_write_config8(dev, SATA_PCS + 1, 0x0F);
  56
  57           /* Setup timings */
  58           pci_write_config16(dev, SATA_PTIM, 0x8000);
  59           pci_write_config16(dev, SATA_STIM, 0x8000);
  60
  61           /* Synchronous DMA */
  62           pci_write_config8(dev, SATA_SYNCC, 0);
  63           pci_write_config16(dev, SATA_SYNCTIM, 0);
  64
  65           /* IDE I/O configuration */
  66           pci_write_config32(dev, SATA_IIOC, 0);
  67
  68           ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
  69           ahci_bar[3] = config->sata_ports_implemented;
  70         } else {
  71           /* SATA configuration */
  72           pci_write_config8(dev, SATA_CMD, 0x07);
  73           pci_write_config8(dev, SATA_PI, 0x8f);
  74
  75           /* Set timings */
  76           pci_write_config16(dev, SATA_PTIM, 0x0a307);
  77           pci_write_config16(dev, SATA_STIM, 0x0a307);
  78
  79           /* Sync DMA */
  80           pci_write_config8(dev, SATA_SYNCC, 0x0f);
  81           pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
  82
  83           /* Fast ATA */
  84           pci_write_config16(dev, SATA_IIOC, 0x1000);
  85
  86           /* Select IDE mode */
  87           pci_write_config8(dev, SATA_MAP, 0x00);
  88
  89           /* Enable ports 0-3 */
  90           pci_write_config8(dev, SATA_PCS + 1, 0x0f);
  91
  92         }
  93
  94         /* secret init sequence, required */
  95         pci_write_config32(dev, 0x94, 0x00400180);
  96         pci_write_config32(dev, 0xa0, 0x18);
  97         pci_write_config32(dev, 0xa4, 0x224);
  98         pci_write_config32(dev, 0xa0, 0x42);
  99         pci_write_config32(dev, 0xa4, 0x22006d);
 100         pci_write_config32(dev, 0xa0, 0x84);
 101         pci_write_config32(dev, 0xa4, 0x24);
 102         pci_write_config32(dev, 0xa0, 0x7a);
 103         pci_write_config32(dev, 0xa4, 0x220000);
 104         pci_write_config32(dev, 0xa0, 0x9c);
 105         pci_write_config32(dev, 0xa4, 0x24);
 106         pci_write_config32(dev, 0xa0, 0x90);
 107         pci_write_config32(dev, 0xa4, 0x220000);
 108         pci_write_config32(dev, 0xa0, 0xa0);
 109         pci_write_config32(dev, 0xa4, 0x12492aa);
 110
 111         printk(BIOS_DEBUG, "SATA Enabled\n");
 112 }
 113
 114 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 115 {
 116         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 117                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 118 }
 119
 120 static struct pci_operations lops_pci = {
 121         .set_subsystem = sata_set_subsystem,
 122 };
 123
 124 static struct device_operations sata_ops  = {
 125         .read_resources   = pci_dev_read_resources,
 126         .set_resources    = pci_dev_set_resources,
 127         .enable_resources = pci_dev_enable_resources,
 128         .init             = sata_init,
 129         .scan_bus         = 0,
 130         .enable           = i3100_enable,
 131         .ops_pci          = &lops_pci,
 132 };
 133
 134 static const struct pci_driver ide_driver __pci_driver = {
 135         .ops    = &sata_ops,
 136         .vendor = PCI_VENDOR_ID_INTEL,
 137         .device = PCI_DEVICE_ID_INTEL_3100_IDE,
 138 };
 139
 140 static const struct pci_driver sata_driver __pci_driver = {
 141         .ops    = &sata_ops,
 142         .vendor = PCI_VENDOR_ID_INTEL,
 143         .device = PCI_DEVICE_ID_INTEL_3100_AHCI,
 144 };
 145
 146 static const struct pci_driver ide_driver_ep80579 __pci_driver = {
 147         .ops    = &sata_ops,
 148         .vendor = PCI_VENDOR_ID_INTEL,
 149         .device = PCI_DEVICE_ID_INTEL_EP80579_IDE,
 150 };
 151
 152 static const struct pci_driver sata_driver_ep80579 __pci_driver = {
 153         .ops    = &sata_ops,
 154         .vendor = PCI_VENDOR_ID_INTEL,
 155         .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI,
 156 };