2 * This file is part of the coreboot project.
4 * Copyright (C) 2004 Linux Networx
5 * Copyright (C) 2008 Arastra, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 /* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */
24 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <device/pci_ops.h>
29 #include <pc80/mc146818rtc.h>
30 #include <pc80/isa-dma.h>
31 #include <pc80/i8259.h>
33 #include <arch/ioapic.h>
40 #define SERIRQ_CNTL 0x64
42 #define GEN_PMCON_1 0xA0
43 #define GEN_PMCON_2 0xA2
44 #define GEN_PMCON_3 0xA4
47 #define MAINBOARD_POWER_OFF 0
48 #define MAINBOARD_POWER_ON 1
50 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
51 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
54 static void i3100_enable_serial_irqs(device_t dev)
56 /* set packet length and toggle silent mode bit */
57 pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
58 pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
61 typedef struct southbridge_intel_i3100_config config_t;
63 static void set_i3100_gpio_use_sel(
64 device_t dev, struct resource *res, config_t *config)
66 u32 gpio_use_sel, gpio_use_sel2;
69 gpio_use_sel = inl(res->base + 0x00) | 0x0000c603;
70 gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100;
71 for (i = 0; i < 64; i++) {
73 switch (config->gpio[i] & I3100_GPIO_USE_MASK) {
74 case I3100_GPIO_USE_AS_NATIVE:
77 case I3100_GPIO_USE_AS_GPIO:
83 /* The caller is responsible for not playing with unimplemented bits */
85 gpio_use_sel &= ~(1 << i);
86 gpio_use_sel |= (val << i);
88 gpio_use_sel2 &= ~(1 << (i - 32));
89 gpio_use_sel2 |= (val << (i - 32));
92 outl(gpio_use_sel, res->base + 0x00);
93 outl(gpio_use_sel2, res->base + 0x30);
96 static void set_i3100_gpio_direction(
97 device_t dev, struct resource *res, config_t *config)
99 u32 gpio_io_sel, gpio_io_sel2;
102 gpio_io_sel = inl(res->base + 0x04);
103 gpio_io_sel2 = inl(res->base + 0x34);
104 for (i = 0; i < 64; i++) {
106 switch (config->gpio[i] & I3100_GPIO_SEL_MASK) {
107 case I3100_GPIO_SEL_OUTPUT:
110 case I3100_GPIO_SEL_INPUT:
116 /* The caller is responsible for not playing with unimplemented bits */
118 gpio_io_sel &= ~(1 << i);
119 gpio_io_sel |= (val << i);
121 gpio_io_sel2 &= ~(1 << (i - 32));
122 gpio_io_sel2 |= (val << (i - 32));
125 outl(gpio_io_sel, res->base + 0x04);
126 outl(gpio_io_sel2, res->base + 0x34);
129 static void set_i3100_gpio_level(
130 device_t dev, struct resource *res, config_t *config)
132 u32 gpio_lvl, gpio_lvl2;
136 gpio_lvl = inl(res->base + 0x0c);
137 gpio_blink = inl(res->base + 0x18);
138 gpio_lvl2 = inl(res->base + 0x38);
139 for (i = 0; i < 64; i++) {
141 switch (config->gpio[i] & I3100_GPIO_LVL_MASK) {
142 case I3100_GPIO_LVL_LOW:
146 case I3100_GPIO_LVL_HIGH:
150 case I3100_GPIO_LVL_BLINK:
157 /* The caller is responsible for not playing with unimplemented bits */
159 gpio_lvl &= ~(1 << i);
160 gpio_blink &= ~(1 << i);
161 gpio_lvl |= (val << i);
162 gpio_blink |= (blink << i);
164 gpio_lvl2 &= ~(1 << (i - 32));
165 gpio_lvl2 |= (val << (i - 32));
168 outl(gpio_lvl, res->base + 0x0c);
169 outl(gpio_blink, res->base + 0x18);
170 outl(gpio_lvl2, res->base + 0x38);
173 static void set_i3100_gpio_inv(
174 device_t dev, struct resource *res, config_t *config)
179 gpio_inv = inl(res->base + 0x2c);
180 for (i = 0; i < 32; i++) {
182 switch (config->gpio[i] & I3100_GPIO_INV_MASK) {
183 case I3100_GPIO_INV_OFF:
186 case I3100_GPIO_INV_ON:
192 gpio_inv &= ~(1 << i);
193 gpio_inv |= (val << i);
195 outl(gpio_inv, res->base + 0x2c);
198 static void i3100_pirq_init(device_t dev)
203 /* Get the chip configuration */
204 config = dev->chip_info;
207 pci_write_config32(dev, 0x60, config->pirq_a_d);
210 pci_write_config32(dev, 0x68, config->pirq_e_h);
212 for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
213 u8 int_pin=0, int_line=0;
215 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
218 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
221 int_line = config->pirq_a_d & 0xff;
225 int_line = (config->pirq_a_d >> 8) & 0xff;
229 int_line = (config->pirq_a_d >> 16) & 0xff;
233 int_line = (config->pirq_a_d >> 24) & 0xff;
240 printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);
241 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
247 static void i3100_power_options(device_t dev) {
250 int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
253 /* Which state do we want to goto after g3 (power restored)?
257 get_option(&pwr_on, "power_on_after_fail");
258 reg8 = pci_read_config8(dev, GEN_PMCON_3);
265 /* avoid #S4 assertions */
267 /* minimum asssertion is 1 to 2 RTCCLK */
269 pci_write_config8(dev, GEN_PMCON_3, reg8);
270 printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
272 /* Set up NMI on errors. */
274 /* Higher Nibble must be 0 */
276 /* IOCHK# NMI Enable */
278 /* PCI SERR# Enable */
279 // reg8 &= ~(1 << 2);
280 /* PCI SERR# Disable for now */
285 nmi_option = NMI_OFF;
286 get_option(&nmi_option, "nmi");
289 printk(BIOS_INFO, "NMI sources enabled.\n");
292 /* Can't mask NMI from PCI-E and NMI_NOW */
293 printk(BIOS_INFO, "NMI sources disabled.\n");
298 // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
299 reg16 = pci_read_config16(dev, GEN_PMCON_1);
300 reg16 &= ~((3 << 0) | (1 << 10));
301 reg16 |= (1 << 3) | (1 << 5);
303 // reg16 |= (1 << 2);
304 pci_write_config16(dev, GEN_PMCON_1, reg16);
306 // Set the board's GPI routing.
307 // i82801gx_gpi_routing(dev);
310 static void i3100_gpio_init(device_t dev)
312 struct resource *res;
315 /* Skip if I don't have any configuration */
316 if (!dev->chip_info) {
319 /* The programmer is responsible for ensuring
320 * a valid gpio configuration.
323 /* Get the chip configuration */
324 config = dev->chip_info;
325 /* Find the GPIO bar */
326 res = find_resource(dev, GPIO_BAR);
331 /* Set the use selects */
332 set_i3100_gpio_use_sel(dev, res, config);
334 /* Set the IO direction */
335 set_i3100_gpio_direction(dev, res, config);
337 /* Setup the input inverters */
338 set_i3100_gpio_inv(dev, res, config);
340 /* Set the value on the GPIO output pins */
341 set_i3100_gpio_level(dev, res, config);
346 static void lpc_init(struct device *dev)
348 struct resource *res;
351 res = find_resource(dev, RCBA);
355 *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0);
357 // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
358 // (register 0x10/0x11) while the old code used int 1 (register 0x12)
360 setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
362 /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
363 pci_write_config32(dev, 0xd0, 0x00000000);
365 i3100_enable_serial_irqs(dev);
367 /* Set up the PIRQ */
368 i3100_pirq_init(dev);
370 /* Setup power options */
371 i3100_power_options(dev);
373 /* Set the state of the gpio lines */
374 i3100_gpio_init(dev);
376 /* Initialize the real time clock */
379 /* Initialize isa dma */
383 i8259_configure_irq_trigger(9, 1);
386 static void i3100_lpc_read_resources(device_t dev)
388 struct resource *res;
390 /* Get the normal pci resources of this device */
391 pci_dev_read_resources(dev);
393 /* Add the ACPI BAR */
394 res = pci_get_resource(dev, ACPI_BAR);
396 /* Add the GPIO BAR */
397 res = pci_get_resource(dev, GPIO_BAR);
399 /* Add an extra subtractive resource for both memory and I/O. */
400 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
403 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
404 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
406 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
407 res->base = 0xff800000;
408 res->size = 0x00800000; /* 8 MB for flash */
409 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
410 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
412 res = new_resource(dev, 3); /* IOAPIC */
413 res->base = IO_APIC_ADDR;
414 res->size = 0x00001000;
415 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
417 /* Add resource for RCBA */
418 res = new_resource(dev, RCBA);
420 res->limit = 0xffffc000;
423 res->flags = IORESOURCE_MEM;
426 static void i3100_lpc_enable_resources(device_t dev)
428 u8 acpi_cntl, gpio_cntl;
430 /* Enable the normal pci resources */
431 pci_dev_enable_resources(dev);
433 /* Enable the ACPI bar */
434 acpi_cntl = pci_read_config8(dev, 0x44);
435 acpi_cntl |= (1 << 7);
436 pci_write_config8(dev, 0x44, acpi_cntl);
438 /* Enable the GPIO bar */
439 gpio_cntl = pci_read_config8(dev, 0x4c);
440 gpio_cntl |= (1 << 4);
441 pci_write_config8(dev, 0x4c, gpio_cntl);
443 /* Enable the RCBA */
444 pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0));
447 static struct pci_operations lops_pci = {
451 static struct device_operations lpc_ops = {
452 .read_resources = i3100_lpc_read_resources,
453 .set_resources = pci_dev_set_resources,
454 .enable_resources = i3100_lpc_enable_resources,
456 .scan_bus = scan_static_bus,
457 .enable = i3100_enable,
458 .ops_pci = &lops_pci,
461 static const struct pci_driver lpc_driver __pci_driver = {
463 .vendor = PCI_VENDOR_ID_INTEL,
464 .device = PCI_DEVICE_ID_INTEL_3100_LPC,
467 static const struct pci_driver lpc_driver_ep80579 __pci_driver = {
469 .vendor = PCI_VENDOR_ID_INTEL,
470 .device = PCI_DEVICE_ID_INTEL_EP80579_LPC,