2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <console/console.h>
28 #include <cpu/x86/cache.h>
29 #include <cpu/x86/smm.h>
33 #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
34 #include "northbridge/intel/sandybridge/sandybridge.h"
37 extern unsigned char _binary_smm_start;
38 extern unsigned char _binary_smm_size;
40 /* While we read PMBASE dynamically in case it changed, let's
41 * initialize it with a sane value
43 static u16 pmbase = DEFAULT_PMBASE;
46 * @brief read and clear PM1_STS
47 * @return PM1_STS register
49 static u16 reset_pm1_status(void)
53 reg16 = inw(pmbase + PM1_STS);
54 /* set status bits are cleared by writing 1 to them */
55 outw(reg16, pmbase + PM1_STS);
60 static void dump_pm1_status(u16 pm1_sts)
62 printk(BIOS_DEBUG, "PM1_STS: ");
63 if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
64 if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
65 if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
66 if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
67 if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
68 if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
69 if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
70 if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
71 printk(BIOS_DEBUG, "\n");
75 * @brief read and clear SMI_STS
76 * @return SMI_STS register
78 static u32 reset_smi_status(void)
82 reg32 = inl(pmbase + SMI_STS);
83 /* set status bits are cleared by writing 1 to them */
84 outl(reg32, pmbase + SMI_STS);
89 static void dump_smi_status(u32 smi_sts)
91 printk(BIOS_DEBUG, "SMI_STS: ");
92 if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
93 if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
94 if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
95 if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
96 if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
97 if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
98 if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
99 if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
100 if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
101 if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
102 if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
103 if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
104 if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
105 if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
106 if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
107 if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
108 if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
109 if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
110 if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
111 if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
112 printk(BIOS_DEBUG, "\n");
117 * @brief read and clear GPE0_STS
118 * @return GPE0_STS register
120 static u32 reset_gpe0_status(void)
124 reg32 = inl(pmbase + GPE0_STS);
125 /* set status bits are cleared by writing 1 to them */
126 outl(reg32, pmbase + GPE0_STS);
131 static void dump_gpe0_status(u32 gpe0_sts)
134 printk(BIOS_DEBUG, "GPE0_STS: ");
135 for (i=31; i<= 16; i--) {
136 if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
138 if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
139 if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
140 if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
141 if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
142 if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
143 if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
144 if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
145 if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
146 if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
147 if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
148 if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
149 if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
150 if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
151 if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
152 printk(BIOS_DEBUG, "\n");
157 * @brief read and clear ALT_GP_SMI_STS
158 * @return ALT_GP_SMI_STS register
160 static u16 reset_alt_gp_smi_status(void)
164 reg16 = inl(pmbase + ALT_GP_SMI_STS);
165 /* set status bits are cleared by writing 1 to them */
166 outl(reg16, pmbase + ALT_GP_SMI_STS);
171 static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
174 printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
175 for (i=15; i<= 0; i--) {
176 if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
178 printk(BIOS_DEBUG, "\n");
184 * @brief read and clear TCOx_STS
185 * @return TCOx_STS registers
187 static u32 reset_tco_status(void)
189 u32 tcobase = pmbase + 0x60;
192 reg32 = inl(tcobase + 0x04);
193 /* set status bits are cleared by writing 1 to them */
194 outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
195 if (reg32 & (1 << 18))
196 outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
202 static void dump_tco_status(u32 tco_sts)
204 printk(BIOS_DEBUG, "TCO_STS: ");
205 if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
206 if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
207 if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
208 if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
209 if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
210 if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
211 if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
212 if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
213 if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
214 if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
215 if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
216 if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
217 if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
218 printk(BIOS_DEBUG, "\n");
224 * @brief Set the EOS bit
226 static void smi_set_eos(void)
230 reg8 = inb(pmbase + SMI_EN);
232 outb(reg8, pmbase + SMI_EN);
235 extern uint8_t smm_relocation_start, smm_relocation_end;
237 static void smm_relocate(void)
243 printk(BIOS_DEBUG, "Initializing SMM handler...");
245 pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
248 printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
250 smi_en = inl(pmbase + SMI_EN);
251 if (smi_en & APMC_EN) {
252 printk(BIOS_INFO, "SMI# handler already enabled?\n");
256 /* copy the SMM relocation code */
257 memcpy((void *)0x38000, &smm_relocation_start,
258 &smm_relocation_end - &smm_relocation_start);
260 printk(BIOS_DEBUG, "\n");
261 dump_smi_status(reset_smi_status());
262 dump_pm1_status(reset_pm1_status());
263 dump_gpe0_status(reset_gpe0_status());
264 dump_alt_gp_smi_status(reset_alt_gp_smi_status());
265 dump_tco_status(reset_tco_status());
267 /* Disable GPE0 PME_B0 */
268 gpe0_en = inl(pmbase + GPE0_EN);
269 gpe0_en &= ~PME_B0_EN;
270 outl(gpe0_en, pmbase + GPE0_EN);
272 /* Enable SMI generation:
274 * - on APMC writes (io 0xb2)
275 * - on writes to SLP_EN (sleep states)
276 * - on writes to GBL_RLS (bios commands)
278 * - on microcontroller writes (io 0x62/0x66)
281 smi_en = 0; /* reset SMI enables */
284 smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
288 #if DEBUG_PERIODIC_SMIS
289 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
292 smi_en |= PERIODIC_EN;
294 smi_en |= SLP_SMI_EN;
299 /* The following need to be on for SMIs to happen */
300 smi_en |= EOS | GBL_SMI_EN;
302 outl(smi_en, pmbase + SMI_EN);
307 outw(pm1_en, pmbase + PM1_EN);
310 * There are several methods of raising a controlled SMI# via
311 * software, among them:
312 * - Writes to io 0xb2 (APMC)
313 * - Writes to the Local Apic ICR with Delivery mode SMI.
315 * Using the local apic is a bit more tricky. According to
316 * AMD Family 11 Processor BKDG no destination shorthand must be
318 * The whole SMM initialization is quite a bit hardware specific, so
319 * I'm not too worried about the better of the methods at the moment
322 /* raise an SMI interrupt */
323 printk(BIOS_SPEW, " ... raise SMI#\n");
327 static int smm_handler_copied = 0;
329 static void smm_install(void)
331 device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
332 u32 smm_base = 0xa0000;
333 struct ied_header ied = {
334 .signature = "INTEL RSVD",
339 /* The first CPU running this gets to copy the SMM handler. But not all
342 if (smm_handler_copied)
344 smm_handler_copied = 1;
346 /* enable the SMM memory window */
347 pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
350 smm_base = pci_read_config32(dev, TSEG) & ~1;
353 /* copy the real SMM handler */
354 printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
355 memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size);
357 /* copy the IED header into place */
358 if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
359 /* Top of TSEG region */
360 smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
361 printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
363 memcpy((void *)smm_base, &ied, sizeof(ied));
367 /* close the SMM memory window and enable normal SMM */
368 pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
373 /* Put SMM code to 0xa0000 */
376 /* Put relocation code to 0x38000 and relocate SMBASE */
379 /* We're done. Make sure SMIs can happen! */
385 /* LOCK the SMM memory window and enable normal SMM.
386 * After running this function, only a full reset can
387 * make the SMM registers writable again.
389 printk(BIOS_DEBUG, "Locking SMM.\n");
390 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
391 D_LCK | G_SMRAME | C_BASE_SEG);
394 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
396 /* The GDT or coreboot table is going to live here. But a long time
397 * after we relocated the GNVS, so this is not troublesome.
399 *(u32 *)0x500 = (u32)gnvs;
400 *(u32 *)0x504 = (u32)tcg;
401 *(u32 *)0x508 = (u32)smi1;