2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pciexp.h>
25 #include <device/pci_ids.h>
28 static u16 pcie_port_link_width(int port)
32 link_width = pci_read_config16(
33 dev_find_slot(0, PCI_DEVFN(0x1c, port)), 0x52);
39 static void pch_pcie_pm_early(struct device *dev)
41 u16 link_width_p0, link_width_p4;
42 u8 slot_power_limit = 10; /* 10W for x1 */
46 link_width_p0 = pcie_port_link_width(0);
47 link_width_p4 = pcie_port_link_width(4);
49 /* Enable dynamic clock gating where needed */
50 reg8 = pci_read_config8(dev, 0xe1);
51 switch (PCI_FUNC(dev->path.pci.devfn)) {
53 if (link_width_p0 == 4)
54 slot_power_limit = 40; /* 40W for x4 */
55 else if (link_width_p0 == 2)
56 slot_power_limit = 20; /* 20W for x2 */
58 if (link_width_p4 == 4)
59 slot_power_limit = 40; /* 40W for x4 */
60 else if (link_width_p4 == 2)
61 slot_power_limit = 20; /* 20W for x2 */
64 case 1: /* Port 1 only if Port 0 is x1 */
65 if (link_width_p0 == 1)
68 case 2: /* Port 2 only if Port 0 is x1 or x2 */
69 case 3: /* Port 3 only if Port 0 is x1 or x2 */
70 if (link_width_p0 <= 2)
73 case 5: /* Port 5 only if Port 4 is x1 */
74 if (link_width_p4 == 1)
77 case 6: /* Port 7 only if Port 4 is x1 or x2 */
78 case 7: /* Port 7 only if Port 4 is x1 or x2 */
79 if (link_width_p4 <= 2)
83 pci_write_config8(dev, 0xe1, reg8);
86 reg32 = pci_read_config32(dev, 0xe8);
88 pci_write_config32(dev, 0xe8, reg32);
90 /* Adjust Common Clock exit latency */
91 reg32 = pci_read_config32(dev, 0xd8);
93 reg32 |= (1 << 16) | (1 << 15);
94 reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
95 pci_write_config32(dev, 0xd8, reg32);
97 /* Adjust ASPM L1 exit latency */
98 reg32 = pci_read_config32(dev, 0x4c);
99 reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
100 if (RCBA32(0x2320) & (1 << 16)) {
101 /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
104 /* Else set ASPM L1 to 2-4us */
107 pci_write_config32(dev, 0x4c, reg32);
109 /* Set slot power limit as configured above */
110 reg32 = pci_read_config32(dev, 0x54);
111 reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */
112 reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */
113 reg32 |= (slot_power_limit << 7);
114 pci_write_config32(dev, 0x54, reg32);
117 static void pch_pcie_pm_late(struct device *dev)
122 /* Set 0x314 = 0x743a361b */
123 pci_mmio_write_config32(dev, 0x314, 0x743a361b);
125 /* Set 0x318[31:16] = 0x1414 */
126 reg32 = pci_mmio_read_config32(dev, 0x318);
129 pci_mmio_write_config32(dev, 0x318, reg32);
131 /* Set 0x324[5] = 1 */
132 reg32 = pci_mmio_read_config32(dev, 0x324);
134 pci_mmio_write_config32(dev, 0x324, reg32);
136 /* Set 0x330[7:0] = 0x40 */
137 reg32 = pci_mmio_read_config32(dev, 0x330);
140 pci_mmio_write_config32(dev, 0x330, reg32);
142 /* Set 0x33C[24:0] = 0x854c74 */
143 reg32 = pci_mmio_read_config32(dev, 0x33c);
146 pci_mmio_write_config32(dev, 0x33c, reg32);
148 /* No IO-APIC, Disable EOI forwarding */
149 reg32 = pci_read_config32(dev, 0xd4);
151 pci_write_config32(dev, 0xd4, reg32);
153 /* Get configured ASPM state */
154 apmc = pci_read_config32(dev, 0x50) & 3;
156 /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
157 if (apmc == PCIE_ASPM_BOTH) {
158 reg32 = pci_read_config32(dev, 0xe8);
160 pci_write_config32(dev, 0xe8, reg32);
164 static void pci_init(struct device *dev)
169 printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
171 /* Enable Bus Master */
172 reg32 = pci_read_config32(dev, PCI_COMMAND);
173 reg32 |= PCI_COMMAND_MASTER;
174 pci_write_config32(dev, PCI_COMMAND, reg32);
176 /* Set Cache Line Size to 0x10 */
177 // This has no effect but the OS might expect it
178 pci_write_config8(dev, 0x0c, 0x10);
180 reg16 = pci_read_config16(dev, 0x3e);
181 reg16 &= ~(1 << 0); /* disable parity error response */
182 // reg16 &= ~(1 << 1); /* disable SERR */
183 reg16 |= (1 << 2); /* ISA enable */
184 pci_write_config16(dev, 0x3e, reg16);
186 #ifdef EVEN_MORE_DEBUG
187 reg32 = pci_read_config32(dev, 0x20);
188 printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
189 reg32 = pci_read_config32(dev, 0x24);
190 printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
191 reg32 = pci_read_config32(dev, 0x28);
192 printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
193 reg32 = pci_read_config32(dev, 0x2c);
194 printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
197 /* Clear errors in status registers */
198 reg16 = pci_read_config16(dev, 0x06);
200 pci_write_config16(dev, 0x06, reg16);
202 reg16 = pci_read_config16(dev, 0x1e);
204 pci_write_config16(dev, 0x1e, reg16);
206 /* Power Management init after enumeration */
207 pch_pcie_pm_late(dev);
210 static void pch_pcie_enable(device_t dev)
212 /* Power Management init before enumeration */
213 pch_pcie_pm_early(dev);
216 static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
218 /* NOTE: This is not the default position! */
219 if (!vendor || !device) {
220 pci_write_config32(dev, 0x94,
221 pci_read_config32(dev, 0));
223 pci_write_config32(dev, 0x94,
224 ((device & 0xffff) << 16) | (vendor & 0xffff));
228 static struct pci_operations pci_ops = {
229 .set_subsystem = pcie_set_subsystem,
232 static struct device_operations device_ops = {
233 .read_resources = pci_bus_read_resources,
234 .set_resources = pci_dev_set_resources,
235 .enable_resources = pci_bus_enable_resources,
237 .enable = pch_pcie_enable,
238 .scan_bus = pciexp_scan_bridge,
242 static const struct pci_driver pch_pcie_port1 __pci_driver = {
244 .vendor = PCI_VENDOR_ID_INTEL,
245 .device = 0x1c10, /* D28:F0 */
248 static const struct pci_driver pch_pcie_port1_a __pci_driver = {
250 .vendor = PCI_VENDOR_ID_INTEL,
251 .device = 0x1e10, /* D28:F0 */
254 static const struct pci_driver pch_pcie_port2 __pci_driver = {
256 .vendor = PCI_VENDOR_ID_INTEL,
257 .device = 0x1c12, /* D28:F1 */
260 static const struct pci_driver pch_pcie_port3 __pci_driver = {
262 .vendor = PCI_VENDOR_ID_INTEL,
263 .device = 0x1c14, /* D28:F2 */
266 static const struct pci_driver pch_pcie_port3_a __pci_driver = {
268 .vendor = PCI_VENDOR_ID_INTEL,
269 .device = 0x1e14, /* D28:F2 */
272 static const struct pci_driver pch_pcie_port4 __pci_driver = {
274 .vendor = PCI_VENDOR_ID_INTEL,
275 .device = 0x1c16, /* D28:F3 */
278 static const struct pci_driver pch_pcie_port4_a __pci_driver = {
280 .vendor = PCI_VENDOR_ID_INTEL,
281 .device = 0x1e16, /* D28:F3 */
284 static const struct pci_driver pch_pcie_port5 __pci_driver = {
286 .vendor = PCI_VENDOR_ID_INTEL,
287 .device = 0x1c18, /* D28:F4 */
290 static const struct pci_driver pch_pcie_port6 __pci_driver = {
292 .vendor = PCI_VENDOR_ID_INTEL,
293 .device = 0x1c1a, /* D28:F5 */
296 static const struct pci_driver pch_pcie_port7 __pci_driver = {
298 .vendor = PCI_VENDOR_ID_INTEL,
299 .device = 0x1c1c, /* D28:F6 */
302 static const struct pci_driver pch_pcie_port8 __pci_driver = {
304 .vendor = PCI_VENDOR_ID_INTEL,
305 .device = 0x1c1e, /* D28:F7 */