2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <pc80/mc146818rtc.h>
26 #include <pc80/isa-dma.h>
27 #include <pc80/i8259.h>
29 #include <arch/ioapic.h>
30 #include <arch/acpi.h>
36 #define ENABLE_ACPI_MODE_IN_COREBOOT 0
37 #define TEST_SMM_FLASH_LOCKDOWN 0
39 typedef struct southbridge_intel_bd82x6x_config config_t;
41 static void pch_enable_apic(struct device *dev)
45 volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
46 volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
48 /* Enable ACPI I/O and power management.
51 pci_write_config8(dev, ACPI_CNTL, 0x80);
54 *ioapic_data = (1 << 25);
56 /* affirm full set of redirection table entries ("write once") */
64 printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
65 if (reg32 != (1 << 25))
68 printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
71 printk(BIOS_SPEW, " reg 0x%04x:", i);
73 printk(BIOS_SPEW, " 0x%08x\n", reg32);
76 *ioapic_index = 3; /* Select Boot Configuration register. */
77 *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
80 static void pch_enable_serial_irqs(struct device *dev)
82 /* Set packet length and toggle silent mode bit for one frame. */
83 pci_write_config8(dev, SERIRQ_CNTL,
84 (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
85 #if !CONFIG_SERIRQ_CONTINUOUS_MODE
86 pci_write_config8(dev, SERIRQ_CNTL,
87 (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
91 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
92 * 0x00 - 0000 = Reserved
93 * 0x01 - 0001 = Reserved
94 * 0x02 - 0010 = Reserved
100 * 0x08 - 1000 = Reserved
102 * 0x0A - 1010 = IRQ10
103 * 0x0B - 1011 = IRQ11
104 * 0x0C - 1100 = IRQ12
105 * 0x0D - 1101 = Reserved
106 * 0x0E - 1110 = IRQ14
107 * 0x0F - 1111 = IRQ15
108 * PIRQ[n]_ROUT[7] - PIRQ Routing Control
109 * 0x80 - The PIRQ is not routed.
112 static void pch_pirq_init(device_t dev)
115 /* Get the chip configuration */
116 config_t *config = dev->chip_info;
118 pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
119 pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
120 pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
121 pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
123 pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
124 pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
125 pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
126 pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
128 /* Eric Biederman once said we should let the OS do this.
129 * I am not so sure anymore he was right.
132 for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
133 u8 int_pin=0, int_line=0;
135 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
138 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
141 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
142 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
143 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
144 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
150 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
154 static void pch_gpi_routing(device_t dev)
156 /* Get the chip configuration */
157 config_t *config = dev->chip_info;
160 /* An array would be much nicer here, or some
161 * other method of doing this.
163 reg32 |= (config->gpi0_routing & 0x03) << 0;
164 reg32 |= (config->gpi1_routing & 0x03) << 2;
165 reg32 |= (config->gpi2_routing & 0x03) << 4;
166 reg32 |= (config->gpi3_routing & 0x03) << 6;
167 reg32 |= (config->gpi4_routing & 0x03) << 8;
168 reg32 |= (config->gpi5_routing & 0x03) << 10;
169 reg32 |= (config->gpi6_routing & 0x03) << 12;
170 reg32 |= (config->gpi7_routing & 0x03) << 14;
171 reg32 |= (config->gpi8_routing & 0x03) << 16;
172 reg32 |= (config->gpi9_routing & 0x03) << 18;
173 reg32 |= (config->gpi10_routing & 0x03) << 20;
174 reg32 |= (config->gpi11_routing & 0x03) << 22;
175 reg32 |= (config->gpi12_routing & 0x03) << 24;
176 reg32 |= (config->gpi13_routing & 0x03) << 26;
177 reg32 |= (config->gpi14_routing & 0x03) << 28;
178 reg32 |= (config->gpi15_routing & 0x03) << 30;
180 pci_write_config32(dev, 0xb8, reg32);
183 static void pch_power_options(device_t dev)
189 /* Get the chip configuration */
190 config_t *config = dev->chip_info;
192 int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
195 /* Which state do we want to goto after g3 (power restored)?
199 * If the option is not existent (Laptops), use Kconfig setting.
201 get_option(&pwr_on, "power_on_after_fail");
203 reg16 = pci_read_config16(dev, GEN_PMCON_3);
206 case MAINBOARD_POWER_OFF:
210 case MAINBOARD_POWER_ON:
214 case MAINBOARD_POWER_KEEP:
216 state = "state keep";
222 reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
223 reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
226 reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
228 reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
230 pci_write_config16(dev, GEN_PMCON_3, reg16);
231 printk(BIOS_INFO, "Set power %s after power failure.\n", state);
233 /* Set up NMI on errors. */
235 reg8 &= 0x0f; /* Higher Nibble must be 0 */
236 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
237 // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
238 reg8 |= (1 << 2); /* PCI SERR# Disable for now */
242 nmi_option = NMI_OFF;
243 get_option(&nmi_option, "nmi");
245 printk(BIOS_INFO, "NMI sources enabled.\n");
246 reg8 &= ~(1 << 7); /* Set NMI. */
248 printk(BIOS_INFO, "NMI sources disabled.\n");
249 reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
253 /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
254 reg16 = pci_read_config16(dev, GEN_PMCON_1);
255 reg16 &= ~(3 << 0); // SMI# rate 1 minute
256 reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
257 #if DEBUG_PERIODIC_SMIS
258 /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
261 reg16 |= (3 << 0); // Periodic SMI every 8s
263 pci_write_config16(dev, GEN_PMCON_1, reg16);
265 // Set the board's GPI routing.
266 pch_gpi_routing(dev);
268 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
270 outl(config->gpe0_en, pmbase + GPE0_EN);
271 outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
273 /* Set up power management block and determine sleep mode */
274 reg32 = inl(pmbase + 0x04); // PM1_CNT
275 reg32 &= ~(7 << 10); // SLP_TYP
276 reg32 |= (1 << 0); // SCI_EN
277 outl(reg32, pmbase + 0x04);
279 /* Clear magic status bits to prevent unexpected wake */
280 reg32 = RCBA32(0x3310);
281 reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
282 RCBA32(0x3310) = reg32;
284 reg32 = RCBA32(0x3f02);
286 RCBA32(0x3f02) = reg32;
289 static void pch_rtc_init(struct device *dev)
294 reg8 = pci_read_config8(dev, GEN_PMCON_3);
295 rtc_failed = reg8 & RTC_BATTERY_DEAD;
297 reg8 &= ~RTC_BATTERY_DEAD;
298 pci_write_config8(dev, GEN_PMCON_3, reg8);
300 printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
302 rtc_init(rtc_failed);
305 static void pch_pm_init(struct device *dev)
307 pci_write_config8(dev, 0xa9, 0x47);
308 RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
309 RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
310 RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
311 RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
312 RCBA32(0x2304) = 0xc0388400;
313 RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
314 RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
315 RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
316 RCBA32(0x3318) = 0x050f0000;
317 RCBA32(0x3324) = 0x04000000;
318 RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
319 RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
320 RCBA32(0x3360) = 0x0001c000;
321 RCBA32(0x3368) = 0x00061100;
322 RCBA32(0x3378) = 0x7f8fdfff;
323 RCBA32(0x337c) = 0x000003fc;
324 RCBA32(0x3388) = 0x00001000;
325 RCBA32(0x3390) = 0x0001c000;
326 RCBA32(0x33a0) = 0x00000800;
327 RCBA32(0x33b0) = 0x00001000;
328 RCBA32(0x33c0) = 0x00093900;
329 RCBA32(0x33cc) = 0x24653002;
330 RCBA32(0x33d0) = 0x062108fe;
331 RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
332 RCBA32(0x3a28) = 0x01010000;
333 RCBA32(0x3a2c) = 0x01010404;
334 RCBA32(0x3a80) = 0x01041041;
335 RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
336 RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
337 RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
338 RCBA32(0x3a6c) = 0x00000001;
339 RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
340 RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
342 RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
345 static void enable_hpet(void)
349 /* Move HPET to default address 0xfed00000 and enable it */
350 reg32 = RCBA32(HPTC);
351 reg32 |= (1 << 7); // HPET Address Enable
353 RCBA32(HPTC) = reg32;
356 static void enable_clock_gating(device_t dev)
361 RCBA32_AND_OR(0x2234, ~0UL, 0xf);
363 reg16 = pci_read_config16(dev, GEN_PMCON_1);
364 reg16 |= (1 << 2) | (1 << 11);
365 pci_write_config16(dev, GEN_PMCON_1, reg16);
367 pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
368 pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
369 pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
370 pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
374 reg32 |= (1 << 29) | (1 << 28);
375 reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
387 RCBA32_OR(0x38c0, 0x7);
388 RCBA32_OR(0x36d4, 0x6680c004);
389 RCBA32_OR(0x3564, 0x3);
392 #if CONFIG_HAVE_SMI_HANDLER
393 static void pch_lock_smm(struct device *dev)
395 #if TEST_SMM_FLASH_LOCKDOWN
399 #if ENABLE_ACPI_MODE_IN_COREBOOT
400 printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
401 outb(0xe1, 0xb2); // Enable ACPI mode
402 printk(BIOS_DEBUG, "done.\n");
404 printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
405 outb(0x1e, 0xb2); // Disable ACPI mode
406 printk(BIOS_DEBUG, "done.\n");
408 /* Don't allow evil boot loaders, kernels, or
409 * userspace applications to deceive us:
413 #if TEST_SMM_FLASH_LOCKDOWN
415 printk(BIOS_DEBUG, "Locking BIOS to RO... ");
416 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
417 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
419 reg8 &= ~(1 << 0); /* clear BIOSWE */
420 pci_write_config8(dev, 0xdc, reg8);
421 reg8 |= (1 << 1); /* set BLE */
422 pci_write_config8(dev, 0xdc, reg8);
423 printk(BIOS_DEBUG, "ok.\n");
424 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
425 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
428 printk(BIOS_DEBUG, "Writing:\n");
429 *(volatile u8 *)0xfff00000 = 0x00;
430 printk(BIOS_DEBUG, "Testing:\n");
431 reg8 |= (1 << 0); /* set BIOSWE */
432 pci_write_config8(dev, 0xdc, reg8);
434 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
435 printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
437 printk(BIOS_DEBUG, "Done.\n");
442 static void pch_disable_smm_only_flashing(struct device *dev)
446 printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
447 reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
449 pci_write_config8(dev, 0xdc, reg8);
452 static void pch_fixups(struct device *dev)
456 /* Indicate DRAM init done for MRC S3 to know it can resume */
457 gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
458 gen_pmcon_2 |= (1 << 7);
459 pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
462 * Enable DMI ASPM in the PCH
464 RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
465 RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
466 RCBA32_OR(0x21a8, 0x3);
469 static void pch_decode_init(struct device *dev)
471 config_t *config = dev->chip_info;
473 printk(BIOS_DEBUG, "pch_decode_init\n");
475 pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
476 pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
477 pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
478 pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
481 static void lpc_init(struct device *dev)
483 printk(BIOS_DEBUG, "pch: lpc_init\n");
485 /* Set the value for PCI command register. */
486 pci_write_config16(dev, PCI_COMMAND, 0x000f);
488 /* IO APIC initialization. */
489 pch_enable_apic(dev);
491 pch_enable_serial_irqs(dev);
493 /* Setup the PIRQ. */
496 /* Setup power options. */
497 pch_power_options(dev);
499 /* Initialize power management */
502 /* Set the state of the GPIO lines. */
505 /* Initialize the real time clock. */
508 /* Initialize ISA DMA. */
511 /* Initialize the High Precision Event Timers, if present. */
514 /* Initialize Clock Gating */
515 enable_clock_gating(dev);
519 /* The OS should do this? */
520 /* Interrupt 9 should be level triggered (SCI) */
521 i8259_configure_irq_trigger(9, 1);
523 pch_disable_smm_only_flashing(dev);
525 #if CONFIG_HAVE_SMI_HANDLER
532 static void pch_lpc_read_resources(device_t dev)
534 struct resource *res;
536 /* Get the normal PCI resources of this device. */
537 pci_dev_read_resources(dev);
539 /* Add an extra subtractive resource for both memory and I/O. */
540 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
543 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
544 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
546 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
547 res->base = 0xff800000;
548 res->size = 0x00800000; /* 8 MB for flash */
549 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
550 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
552 res = new_resource(dev, 3); /* IOAPIC */
553 res->base = IO_APIC_ADDR;
554 res->size = 0x00001000;
555 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
558 static void pch_lpc_enable_resources(device_t dev)
560 pch_decode_init(dev);
561 return pci_dev_enable_resources(dev);
564 static void pch_lpc_enable(device_t dev)
566 /* Enable PCH Display Port */
567 RCBA16(DISPBDF) = 0x0010;
568 RCBA32_OR(FD2, PCH_ENABLE_DBDF);
573 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
575 if (!vendor || !device) {
576 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
577 pci_read_config32(dev, PCI_VENDOR_ID));
579 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
580 ((device & 0xffff) << 16) | (vendor & 0xffff));
584 static struct pci_operations pci_ops = {
585 .set_subsystem = set_subsystem,
588 static struct device_operations device_ops = {
589 .read_resources = pch_lpc_read_resources,
590 .set_resources = pci_dev_set_resources,
591 .enable_resources = pch_lpc_enable_resources,
593 .enable = pch_lpc_enable,
594 .scan_bus = scan_static_bus,
599 /* IDs for LPC device of Intel 6 series Chipset and
600 * Intel C200 Series Chipset according to specification
601 * update from August 2011
604 static const struct pci_driver q67_lpc __pci_driver = {
606 .vendor = PCI_VENDOR_ID_INTEL,
609 static const struct pci_driver q65_lpc __pci_driver = {
611 .vendor = PCI_VENDOR_ID_INTEL,
614 static const struct pci_driver b65_lpc __pci_driver = {
616 .vendor = PCI_VENDOR_ID_INTEL,
619 static const struct pci_driver h67_lpc __pci_driver = {
621 .vendor = PCI_VENDOR_ID_INTEL,
624 static const struct pci_driver z68_lpc __pci_driver = {
626 .vendor = PCI_VENDOR_ID_INTEL,
629 static const struct pci_driver h61_lpc __pci_driver = {
631 .vendor = PCI_VENDOR_ID_INTEL,
634 static const struct pci_driver c202_lpc __pci_driver = {
636 .vendor = PCI_VENDOR_ID_INTEL,
639 static const struct pci_driver c204_lpc __pci_driver = {
641 .vendor = PCI_VENDOR_ID_INTEL,
644 static const struct pci_driver c206_lpc __pci_driver = {
646 .vendor = PCI_VENDOR_ID_INTEL,
649 static const struct pci_driver qm67_lpc __pci_driver = {
651 .vendor = PCI_VENDOR_ID_INTEL,
654 static const struct pci_driver um67_lpc __pci_driver = {
656 .vendor = PCI_VENDOR_ID_INTEL,
659 static const struct pci_driver hm67_lpc __pci_driver = {
661 .vendor = PCI_VENDOR_ID_INTEL,
664 static const struct pci_driver hm65_lpc __pci_driver = {
666 .vendor = PCI_VENDOR_ID_INTEL,
669 static const struct pci_driver qs67_lpc __pci_driver = {
671 .vendor = PCI_VENDOR_ID_INTEL,
674 static const struct pci_driver c216_lpc __pci_driver = {
676 .vendor = PCI_VENDOR_ID_INTEL,