2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 #include <arch/romcc_io.h>
25 #include <console/console.h>
27 #include <device/pci_ids.h>
32 static const char *me_ack_values[] = {
33 [ME_HFS_ACK_NO_DID] = "No DID Ack received",
34 [ME_HFS_ACK_RESET] = "Non-power cycle reset",
35 [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset",
36 [ME_HFS_ACK_S3] = "Go to S3",
37 [ME_HFS_ACK_S4] = "Go to S4",
38 [ME_HFS_ACK_S5] = "Go to S5",
39 [ME_HFS_ACK_GBL_RESET] = "Global Reset",
40 [ME_HFS_ACK_CONTINUE] = "Continue to boot"
43 static inline void pci_read_dword_ptr(void *ptr, int offset)
45 u32 dword = pci_read_config32(PCH_ME_DEV, offset);
46 memcpy(ptr, &dword, sizeof(dword));
49 static inline void pci_write_dword_ptr(void *ptr, int offset)
52 memcpy(&dword, ptr, sizeof(dword));
53 pci_write_config32(PCH_ME_DEV, offset, dword);
56 void intel_early_me_status(void)
61 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
62 pci_read_dword_ptr(&gmes, PCI_ME_GMES);
64 intel_me_status(&hfs, &gmes);
67 int intel_early_me_init(void)
73 printk(BIOS_INFO, "Intel ME early init\n");
75 /* Wait for ME UMA SIZE VALID bit to be set */
76 for (count = ME_RETRY; count > 0; --count) {
77 pci_read_dword_ptr(&uma, PCI_ME_UMA);
83 printk(BIOS_ERR, "ERROR: ME is not ready!\n");
87 /* Check for valid firmware */
88 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
90 printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
94 printk(BIOS_INFO, "Intel ME firmware is ready\n");
98 int intel_early_me_uma_size(void)
102 pci_read_dword_ptr(&uma, PCI_ME_UMA);
104 printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
108 printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
112 static inline void set_global_reset(int enable)
114 u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
116 /* Clear CF9 Without Resume Well Reset Enable */
117 etr3 &= ~ETR3_CWORWRE;
119 /* CF9GR indicates a Global Reset */
125 pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
128 int intel_early_me_init_done(u8 status)
132 u32 mebase_l, mebase_h;
134 struct me_did did = {
135 .init_done = ME_INIT_DONE,
139 /* MEBASE from MESEG_BASE[35:20] */
140 mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
141 mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
142 did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
144 /* Send message to ME */
145 printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
146 "UMA base: 0x%04x\n", status, did.uma_base);
148 pci_write_dword_ptr(&did, PCI_ME_H_GS);
150 /* Must wait for ME acknowledgement */
151 for (count = ME_RETRY; count > 0; --count) {
152 pci_read_dword_ptr(&hfs, PCI_ME_HFS);
153 if (hfs.bios_msg_ack)
158 printk(BIOS_ERR, "ERROR: ME failed to respond\n");
162 /* Return the requested BIOS action */
163 printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
164 me_ack_values[hfs.ack_data]);
166 /* Check status after acknowledgement */
167 intel_early_me_status();
170 switch (hfs.ack_data) {
171 case ME_HFS_ACK_CONTINUE:
172 /* Continue to boot */
174 case ME_HFS_ACK_RESET:
175 /* Non-power cycle reset */
179 case ME_HFS_ACK_PWR_CYCLE:
180 /* Power cycle reset */
184 case ME_HFS_ACK_GBL_RESET:
195 /* Perform the requested reset */