2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 /* Global Variables */
24 Name(\PICM, 0) // IOAPIC/8259
25 Name(\DSEN, 1) // Display Output Switching Enable
27 /* Global ACPI memory region. This region is used for passing information
28 * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
29 * Since we don't know where this will end up in memory at ACPI compile time,
30 * we have to fix it up in coreboot's ACPI creation phase.
34 OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
35 Field (GNVS, ByteAcc, NoLock, Preserve)
39 OSYS, 16, // 0x00 - Operating System
40 SMIF, 8, // 0x02 - SMI function
41 PRM0, 8, // 0x03 - SMI function parameter
42 PRM1, 8, // 0x04 - SMI function parameter
43 SCIF, 8, // 0x05 - SCI function
44 PRM2, 8, // 0x06 - SCI function parameter
45 PRM3, 8, // 0x07 - SCI function parameter
46 LCKF, 8, // 0x08 - Global Lock function for EC
47 PRM4, 8, // 0x09 - Lock function parameter
48 PRM5, 8, // 0x0a - Lock function parameter
49 P80D, 32, // 0x0b - Debug port (IO 0x80) value
50 LIDS, 8, // 0x0f - LID state (open = 1)
51 PWRS, 8, // 0x10 - Power State (AC = 1)
54 TLVL, 8, // 0x11 - Throttle Level Limit
55 FLVL, 8, // 0x12 - Current FAN Level
56 TCRT, 8, // 0x13 - Critical Threshold
57 TPSV, 8, // 0x14 - Passive Threshold
58 TMAX, 8, // 0x15 - CPU Tj_max
59 F0OF, 8, // 0x16 - FAN 0 OFF Threshold
60 F0ON, 8, // 0x17 - FAN 0 ON Threshold
61 F0PW, 8, // 0x18 - FAN 0 PWM value
62 F1OF, 8, // 0x19 - FAN 1 OFF Threshold
63 F1ON, 8, // 0x1a - FAN 1 ON Threshold
64 F1PW, 8, // 0x1b - FAN 1 PWM value
65 F2OF, 8, // 0x1c - FAN 2 OFF Threshold
66 F2ON, 8, // 0x1d - FAN 2 ON Threshold
67 F2PW, 8, // 0x1e - FAN 2 PWM value
68 F3OF, 8, // 0x1f - FAN 3 OFF Threshold
69 F3ON, 8, // 0x20 - FAN 3 ON Threshold
70 F3PW, 8, // 0x21 - FAN 3 PWM value
71 F4OF, 8, // 0x22 - FAN 4 OFF Threshold
72 F4ON, 8, // 0x23 - FAN 4 ON Threshold
73 F4PW, 8, // 0x24 - FAN 4 PWM value
74 /* Processor Identification */
76 APIC, 8, // 0x28 - APIC Enabled by coreboot
77 MPEN, 8, // 0x29 - Multi Processor Enable
78 PCP0, 8, // 0x2a - PDC CPU/CORE 0
79 PCP1, 8, // 0x2b - PDC CPU/CORE 1
80 PPCM, 8, // 0x2c - Max. PPC state
81 PCNT, 8, // 0x2d - Processor count
82 /* Super I/O & CMOS config */
85 S5U0, 8, // 0x32 - Enable USB0 in S5
86 S5U1, 8, // 0x33 - Enable USB1 in S5
87 S3U0, 8, // 0x35 - Enable USB0 in S3
88 S3U1, 8, // 0x36 - Enable USB1 in S3
89 S33G, 8, // 0x37 - Enable 3G in S3
90 CMEM, 32, // 0x38 - CBMEM TOC
91 /* Integrated Graphics Device */
93 IGDS, 8, // 0x3c - IGD state (primary = 1)
94 TLST, 8, // 0x3d - Display Toggle List pointer
95 CADL, 8, // 0x3e - Currently Attached Devices List
96 PADL, 8, // 0x3f - Previously Attached Devices List
97 CSTE, 16, // 0x40 - Current display state
98 NSTE, 16, // 0x42 - Next display state
99 SSTE, 16, // 0x44 - Set display state
101 NDID, 8, // 0x46 - Number of Device IDs
102 DID1, 32, // 0x47 - Device ID 1
103 DID2, 32, // 0x4b - Device ID 2
104 DID3, 32, // 0x4f - Device ID 3
105 DID4, 32, // 0x53 - Device ID 4
106 DID5, 32, // 0x57 - Device ID 5
107 /* Backlight Control */
109 BLCS, 8, // 0x64 - Backlight control possible?
110 BRTL, 8, // 0x65 - Brightness Level
112 /* Ambient Light Sensors */
114 ALSE, 8, // 0x6e - ALS enable
115 ALAF, 8, // 0x6f - Ambient light adjustment factor
116 LLOW, 8, // 0x70 - LUX Low
117 LHIH, 8, // 0x71 - LUX High
120 EMAE, 8, // 0x78 - EMA enable
121 EMAP, 16, // 0x79 - EMA pointer
122 EMAL, 16, // 0x7b - EMA length
125 MEFE, 8, // 0x82 - MEF enable
128 TPMP, 8, // 0x8c - TPM
129 TPME, 8, // 0x8d - TPM enable
132 GTF0, 56, // 0x96 - GTF task file buffer for port 0
133 GTF1, 56, // 0x9d - GTF task file buffer for port 1
134 GTF2, 56, // 0xa4 - GTF task file buffer for port 2
135 IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
136 IDET, 8, // 0xac - IDE
139 ASLB, 32, // 0xb4 - IGD OpRegion Base Address
140 IBTT, 8, // 0xb8 - IGD boot panel device
141 IPAT, 8, // 0xb9 - IGD panel type cmos option
142 ITVF, 8, // 0xba - IGD TV format cmos option
143 ITVM, 8, // 0xbb - IGD TV minor format option
144 IPSC, 8, // 0xbc - IGD panel scaling
145 IBLC, 8, // 0xbd - IGD BLC config
146 IBIA, 8, // 0xbe - IGD BIA config
147 ISSC, 8, // 0xbf - IGD SSC config
148 I409, 8, // 0xc0 - IGD 0409 modified settings
149 I509, 8, // 0xc1 - IGD 0509 modified settings
150 I609, 8, // 0xc2 - IGD 0609 modified settings
151 I709, 8, // 0xc3 - IGD 0709 modified settings
152 IDMM, 8, // 0xc4 - IGD DVMT Mode
153 IDMS, 8, // 0xc5 - IGD DVMT memory size
154 IF1E, 8, // 0xc6 - IGD function 1 enable
155 HVCO, 8, // 0xc7 - IGD HPLL VCO
156 NXD1, 32, // 0xc8 - IGD _DGS next DID1
157 NXD2, 32, // 0xcc - IGD _DGS next DID2
158 NXD3, 32, // 0xd0 - IGD _DGS next DID3
159 NXD4, 32, // 0xd4 - IGD _DGS next DID4
160 NXD5, 32, // 0xd8 - IGD _DGS next DID5
161 NXD6, 32, // 0xdc - IGD _DGS next DID6
162 NXD7, 32, // 0xe0 - IGD _DGS next DID7
163 NXD8, 32, // 0xe4 - IGD _DGS next DID8
165 /* ChromeOS specific */
167 #include <vendorcode/google/chromeos/acpi/gnvs.asl>
171 /* Set flag to enable USB charging in S3 */
178 /* Set flag to disable USB charging in S3 */
185 /* Set flag to enable USB charging in S5 */
192 /* Set flag to disable USB charging in S5 */
199 /* Set flag to enable 3G module in S3 */
205 /* Set flag to disable 3G module in S3 */
211 /* Update Fan 0 thresholds */
218 /* Update Fan 1 thresholds */
225 /* Update Fan 2 thresholds */
232 /* Update Fan 3 thresholds */
239 /* Update Fan 4 thresholds */