2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2011 Google Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 config SOUTHBRIDGE_INTEL_BD82X6X
23 config SOUTHBRIDGE_INTEL_C216
26 if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
28 config SOUTH_BRIDGE_OPTIONS # dummy
31 select HAVE_HARD_RESET
33 select USE_WATCHDOG_ON_BOOT
35 select PCIEXP_COMMON_CLOCK
41 config EHCI_DEBUG_OFFSET
45 config BOOTBLOCK_SOUTHBRIDGE_INIT
47 default "southbridge/intel/bd82x6x/bootblock.c"
49 config SERIRQ_CONTINUOUS_MODE
53 If you set this option to y, the serial IRQ machine will be
54 operated in continuous mode.
58 if SOUTHBRIDGE_INTEL_BD82X6X
61 default "Cougar Point"
64 if SOUTHBRIDGE_INTEL_C216
67 default "Panther Point"