src/southbridge/broadcom/bcm5785/bcm5785_sata.c

   1 /*
   2  * Copyright  2005 AMD
   3  *  by yinghai.lu@amd.com
   4  */
   5
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <delay.h>
   9 #include <device/pci.h>
  10 #include <device/pci_ids.h>
  11 #include <device/pci_ops.h>
  12 #include <arch/io.h>
  13 #include "bcm5785.h"
  14
  15
  16 static void sata_init(struct device *dev)
  17 {
  18
  19         uint8_t byte;
  20
  21         uint8_t *base;
  22         uint8_t *mmio;
  23         struct resource *res;
  24         unsigned int mmio_base;
  25         volatile unsigned int *mmio_reg;
  26         int i;
  27
  28         if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
  29                 byte = pci_read_config8(dev, 0x78);
  30                 byte |= (1<<7);
  31                 pci_write_config8(dev, 0x78, byte);
  32
  33                 res = find_resource(dev, 0x24);
  34                 base = res->base;
  35
  36                 mmio_base = base;
  37                 mmio_base &= 0xfffffffc;
  38                 mmio_reg = (unsigned int *)( mmio_base + 0x10f0 );
  39                 * mmio_reg = 0x40000001;
  40                 mmio_reg = ( unsigned int *)( mmio_base + 0x8c );
  41                 * mmio_reg = 0x00ff2007;
  42                 mdelay( 10 );
  43                 * mmio_reg = 0x78592009;
  44                 mdelay( 10 );
  45                 * mmio_reg = 0x00082004;
  46                 mdelay( 10 );
  47                 * mmio_reg = 0x00002004;
  48                 mdelay( 10 );
  49
  50                 //init PHY
  51
  52                 printk_debug("init PHY...\n");
  53                 for(i=0; i<4; i++) {
  54                         mmio = base + 0x100 * i;
  55                         byte = read8(mmio + 0x40);
  56                         printk_debug("port %d PHY status = %02x\r\n", i, byte);
  57                         if(byte & 0x4) {// bit 2 is set
  58                                 byte = read8(mmio+0x48);
  59                                 write8(mmio + 0x48, byte | 1);
  60                                 write8(mmio + 0x48, byte & (~1));
  61                                 byte = read8(mmio + 0x40);
  62                                 printk_debug("after reset port %d PHY status = %02x\r\n", i, byte);
  63                         }
  64                 }
  65
  66         }
  67
  68
  69 }
  70
  71 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  72 {
  73         pci_write_config32(dev, 0x40,
  74                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  75 }
  76 static struct pci_operations lops_pci = {
  77         .set_subsystem = lpci_set_subsystem,
  78 };
  79
  80 static struct device_operations sata_ops  = {
  81         .read_resources   = pci_dev_read_resources,
  82         .set_resources    = pci_dev_set_resources,
  83         .enable_resources = pci_dev_enable_resources,
  84 //      .enable           = bcm5785_enable,
  85         .init             = sata_init,
  86         .scan_bus         = 0,
  87         .ops_pci          = &lops_pci,
  88 };
  89
  90 static const struct pci_driver sata0_driver __pci_driver = {
  91         .ops    = &sata_ops,
  92         .vendor = PCI_VENDOR_ID_SERVERWORKS,
  93         .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA,
  94 };
  95