2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 AMD
5 * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #define PCI_DEV(BUS, DEV, FN) ( \
25 (((BUS) & 0xFFF) << 20) | \
26 (((DEV) & 0x1F) << 15) | \
29 typedef unsigned device_t;
31 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
34 addr = (dev>>4) | where;
35 outl(0x80000000 | (addr & ~3), 0xCF8);
39 static unsigned pci_read_config32(device_t dev, unsigned where)
42 addr = (dev>>4) | where;
43 outl(0x80000000 | (addr & ~3), 0xCF8);
47 #include "../../../northbridge/amd/amdk8/reset_test.c"
52 /* Try rebooting through port 0xcf9 */
53 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
54 outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
55 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);