3 * by yinghai.lu@amd.com
9 #define PCI_DEV(BUS, DEV, FN) ( \
10 (((BUS) & 0xFFF) << 20) | \
11 (((DEV) & 0x1F) << 15) | \
14 typedef unsigned device_t;
16 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
19 addr = (dev>>4) | where;
20 outl(0x80000000 | (addr & ~3), 0xCF8);
24 static unsigned pci_read_config32(device_t dev, unsigned where)
27 addr = (dev>>4) | where;
28 outl(0x80000000 | (addr & ~3), 0xCF8);
32 #include "../../../northbridge/amd/amdk8/reset_test.c"
37 /* Try rebooting through port 0xcf9 */
38 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
39 outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
40 outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);