2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
29 static int sata_drive_detect(int portnum, u16 iobar)
33 outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
34 while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
35 (byte != (0xA0 + 0x10 * (portnum % 2))) ||
36 ((byte2 & 0x88) != 0)) {
37 printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
38 if (byte != (0xA0 + 0x10 * (portnum % 2))) {
39 /* This will happen at the first iteration of this loop
40 * if the first SATA port is unpopulated and the
41 * second SATA port is poulated.
43 printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
44 "retrying init\n", i * 10);
47 printk(BIOS_SPEW, "drive detection not yet completed, "
52 printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
56 static const u32 sata_phy[][3] = {
57 {0x0056A607, 0x00061400, 0x00061302}, /* port 0 */
58 {0x0056A607, 0x00061400, 0x00061302}, /* port 1 */
59 {0x0056A607, 0x00061402, 0x00064300}, /* port 2 */
60 {0x0056A607, 0x00061402, 0x00064300}, /* port 3 */
61 {0x0056A700, 0x00061502, 0x00064302}, /* port 4 */
62 {0x0056A700, 0x00061502, 0x00064302} /* port 5 */
65 static void sata_init(struct device *dev)
72 u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
75 struct southbridge_ati_sb800_config *conf;
76 conf = dev->chip_info;
79 /* SATA SMBus Disable */
80 /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
81 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
84 rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
86 /* get base addresss */
87 sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
88 sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
89 sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
90 sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
91 sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
92 sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
94 printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
95 printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */
96 printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
97 printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
98 printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
99 printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
102 word = pci_read_config16(dev, 0x04);
104 pci_write_config16(dev, 0x04, word);
106 /* Set SATA Operation Mode, Set to IDE mode */
107 byte = pci_read_config8(dev, 0x40);
110 pci_write_config8(dev, 0x40, byte);
113 pci_write_config32(dev, 0x8, dword);
115 /* Program the 2C to 0x43801002 */
117 pci_write_config32(dev, 0x2c, dword);
119 pci_write_config8(dev, 0x34, 0x70); /* 8.11 SATA MSI and D3 Power State Capability */
121 dword = read32(sata_bar5 + 0xFC);
122 dword &= ~(1 << 11); /* rpr 8.8. Disabling Aggressive Link Power Management */
123 dword &= ~(1 << 12); /* rpr 8.9.1 Disabling Port Multiplier support. */
124 dword &= ~(1 << 10); /* rpr 8.9.2 disabling FIS-based Switching support */
125 dword &= ~(1 << 19); /* rpr 8.10. Disabling CCC (Command Completion Coalescing) Support */
126 write32((sata_bar5 + 0xFC), dword);
128 dword = read32(sata_bar5 + 0xF8);
129 dword &= ~(0x3F << 22); /* rpr 8.9.2 disabling FIS-based Switching support */
130 write32(sata_bar5 + 0xF8, dword);
132 byte = pci_read_config8(dev, 0x40);
134 pci_write_config8(dev, 0x40, byte);
137 printk(BIOS_SPEW, "rev_id=%x\n", rev_id);
138 dword = pci_read_config32(dev, 0x84);
139 if (rev_id == 0x11) /* A11 */
141 pci_write_config32(dev, 0x84, dword);
143 /* rpr8.12 Program the watchdog counter to 0x20 */
144 byte = pci_read_config8(dev, 0x44);
146 pci_write_config8(dev, 0x44, byte);
148 pci_write_config8(dev, 0x46, 0x20);
152 for (i = 0; i < 6; i++) {
153 pci_write_config16(dev, 0x84, 0x3006 | i << 9);
154 pci_write_config32(dev, 0x94, sata_phy[i][0]); /* Gen 3 */
155 pci_write_config16(dev, 0x84, 0x2006 | i << 9);
156 pci_write_config32(dev, 0x94, sata_phy[i][1]); /* Gen 2 */
157 pci_write_config16(dev, 0x84, 0x1006 | i << 9);
158 pci_write_config32(dev, 0x94, sata_phy[i][2]); /* Gen 1 */
161 /* Enable the I/O, MM, BusMaster access for SATA */
162 byte = pci_read_config8(dev, 0x4);
164 pci_write_config8(dev, 0x4, byte);
166 /* RPR7.7 SATA drive detection. */
167 /* Use BAR5+0x128,BAR0 for Primary Slave */
168 /* Use BAR5+0x1A8,BAR0 for Primary Slave */
169 /* Use BAR5+0x228,BAR2 for Secondary Master */
170 /* Use BAR5+0x2A8,BAR2 for Secondary Slave */
171 /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
172 /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
174 /* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
176 for (i = 0; i < 4; i++) {
177 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
178 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
181 /* If the drive status is 0x1 then we see it but we aren't talking to it. */
182 /* Try to do something about it. */
183 printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
185 /* Read in Port-N Serial ATA Control Register */
186 byte = read8(sata_bar5 + 0x12C + 0x80 * i);
188 /* Set Reset Bit and 1.5g bit */
190 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
195 /* Clear Reset Bit */
197 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
203 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
204 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
209 for (j = 0; j < 10; j++) {
210 if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
213 printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
214 (i / 2) ? "Secondary" : "Primary",
215 (i % 2 ) ? "Slave" : "Master",
216 (j == 10) ? "not " : "",
217 (j == 10) ? j : j + 1);
219 printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
220 (i / 2) ? "Secondary" : "Primary",
221 (i % 2 ) ? "Slave" : "Master", i);
225 /* Below is CIM InitSataLateFar */
226 /* Enable interrupts from the HBA */
227 byte = read8(sata_bar5 + 0x4);
229 write8((sata_bar5 + 0x4), byte);
231 /* Clear error status */
232 write32((sata_bar5 + 0x130), 0xFFFFFFFF);
233 write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
234 write32((sata_bar5 + 0x230), 0xFFFFFFFF);
235 write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
236 write32((sata_bar5 + 0x330), 0xFFFFFFFF);
237 write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
239 /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
240 /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
243 /* word = pm_ioread(0x28); */
244 /* byte = pm_ioread(0x29); */
245 /* word |= byte<<8; */
246 /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
247 /* write32(word, 0x80000000); */
250 static struct pci_operations lops_pci = {
251 /* .set_subsystem = pci_dev_set_subsystem, */
254 static struct device_operations sata_ops = {
255 .read_resources = pci_dev_read_resources,
256 .set_resources = pci_dev_set_resources,
257 .enable_resources = pci_dev_enable_resources,
260 .ops_pci = &lops_pci,
263 static const struct pci_driver sata0_driver __pci_driver = {
265 .vendor = PCI_VENDOR_ID_ATI,
266 .device = PCI_DEVICE_ID_ATI_SB800_SATA,