2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _SB700_SMBUS_C_
21 #define _SB700_SMBUS_C_
25 static inline void smbus_delay(void)
27 outb(inb(0x80), 0x80);
30 static int smbus_wait_until_ready(u32 smbus_io_base)
33 loops = SMBUS_TIMEOUT;
36 val = inb(smbus_io_base + SMBHSTSTAT);
38 if (val == 0) { /* ready now */
41 outb(val, smbus_io_base + SMBHSTSTAT);
43 return -2; /* time out */
46 static int smbus_wait_until_done(u32 smbus_io_base)
49 loops = SMBUS_TIMEOUT;
53 val = inb(smbus_io_base + SMBHSTSTAT);
54 val &= 0x1f; /* mask off reserved bits */
56 return -5; /* error */
59 outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
63 return -3; /* timeout */
66 int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
70 if (smbus_wait_until_ready(smbus_io_base) < 0) {
71 return -2; /* not ready */
74 /* set the device I'm talking too */
75 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
77 byte = inb(smbus_io_base + SMBHSTCTRL);
78 byte &= 0xe3; /* Clear [4:2] */
79 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
80 outb(byte, smbus_io_base + SMBHSTCTRL);
82 /* poll for transaction completion */
83 if (smbus_wait_until_done(smbus_io_base) < 0) {
84 return -3; /* timeout or error */
87 /* read results of transaction */
88 byte = inb(smbus_io_base + SMBHSTCMD);
93 int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
97 if (smbus_wait_until_ready(smbus_io_base) < 0) {
98 return -2; /* not ready */
101 /* set the command... */
102 outb(val, smbus_io_base + SMBHSTCMD);
104 /* set the device I'm talking too */
105 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
107 byte = inb(smbus_io_base + SMBHSTCTRL);
108 byte &= 0xe3; /* Clear [4:2] */
109 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
110 outb(byte, smbus_io_base + SMBHSTCTRL);
112 /* poll for transaction completion */
113 if (smbus_wait_until_done(smbus_io_base) < 0) {
114 return -3; /* timeout or error */
120 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
124 if (smbus_wait_until_ready(smbus_io_base) < 0) {
125 return -2; /* not ready */
128 /* set the command/address... */
129 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
131 /* set the device I'm talking too */
132 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
134 byte = inb(smbus_io_base + SMBHSTCTRL);
135 byte &= 0xe3; /* Clear [4:2] */
136 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
137 outb(byte, smbus_io_base + SMBHSTCTRL);
139 /* poll for transaction completion */
140 if (smbus_wait_until_done(smbus_io_base) < 0) {
141 return -3; /* timeout or error */
144 /* read results of transaction */
145 byte = inb(smbus_io_base + SMBHSTDAT0);
150 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
154 if (smbus_wait_until_ready(smbus_io_base) < 0) {
155 return -2; /* not ready */
158 /* set the command/address... */
159 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
161 /* set the device I'm talking too */
162 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
165 outb(val, smbus_io_base + SMBHSTDAT0);
167 byte = inb(smbus_io_base + SMBHSTCTRL);
168 byte &= 0xe3; /* Clear [4:2] */
169 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
170 outb(byte, smbus_io_base + SMBHSTCTRL);
172 /* poll for transaction completion */
173 if (smbus_wait_until_done(smbus_io_base) < 0) {
174 return -3; /* timeout or error */
180 static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
184 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
187 * For certain revisions of the chip, the ABCFG registers,
188 * with an address of 0x100NN (where 'N' is any hexadecimal
189 * number), require an extra programming step.*/
190 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
195 /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
196 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
198 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
201 /* space = 0: AX_INDXC, AX_DATAC
202 * space = 1: AX_INDXP, AX_DATAP
204 static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
209 /* read axindc to tmp */
210 outl(space << 30 | space << 3 | 0x30, AB_INDX);
211 outl(axindc, AB_DATA);
212 outl(space << 30 | space << 3 | 0x34, AB_INDX);
219 outl(space << 30 | space << 3 | 0x30, AB_INDX);
220 outl(axindc, AB_DATA);
221 outl(space << 30 | space << 3 | 0x34, AB_INDX);