2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ids.h>
24 #include <device/pci_ops.h>
25 #include <device/smbus.h>
26 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
30 #include <arch/ioapic.h>
37 #define MAINBOARD_POWER_OFF 0
38 #define MAINBOARD_POWER_ON 1
40 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
45 * SB700 enables all USB controllers by default in SMBUS Control.
46 * SB700 enables SATA by default in SMBUS Control.
48 static void sm_init(device_t dev)
58 printk(BIOS_INFO, "sm_init().\n");
60 rev = get_sb700_revision(dev);
61 ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */
62 /* Don't rename APIC ID */
63 /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
64 * We need to check out why and change back. */
65 clear_ioapic(ioapic_base);
67 /* 2.10 Interrupt Routing/Filtering */
68 dword = pci_read_config8(dev, 0x62);
70 pci_write_config8(dev, 0x62, dword);
72 /* Delay back to back interrupts to the CPU. */
73 dword = pci_read_config16(dev, 0x64);
75 pci_write_config16(dev, 0x64, dword);
77 /* rrg:K8 INTR Enable (BIOS should set this bit after PIC initialization) */
78 /* rpr 2.1 Enabling Legacy Interrupt */
79 dword = pci_read_config8(dev, 0x62);
81 pci_write_config8(dev, 0x62, dword);
83 dword = pci_read_config32(dev, 0x78);
85 pci_write_config32(dev, 0x78, dword); /* enable 0xCD6 0xCD7 */
87 /* bit 10: MultiMediaTimerIrqEn */
88 dword = pci_read_config8(dev, 0x64);
90 pci_write_config8(dev, 0x64, dword);
91 /* enable serial irq */
92 byte = pci_read_config8(dev, 0x69);
93 byte |= 1 << 7; /* enable serial irq function */
95 byte |= 4 << 2; /* set NumSerIrqBits=4 */
96 pci_write_config8(dev, 0x69, byte);
99 * Note: These 2 registers need to be set correctly for the S-state
100 * to work properly. Otherwise the system may hang during resume
103 /*Use 8us clock for delays in the S-state resume timing sequence.*/
104 byte = pm_ioread(0x65);
106 pm_iowrite(0x65, byte);
107 /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */
108 byte = pm_ioread(0x68);
110 pm_iowrite(0x68, byte);
113 byte = pci_read_config8(dev, 0x41);
115 pci_write_config8(dev, 0x41, byte);
117 byte = pm_ioread(0x61);
118 byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */
119 pm_iowrite(0x61, byte);
122 byte = pm_ioread(0x53);
124 pm_iowrite(0x53, byte);
126 /* power after power fail */
127 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
128 get_option(&on, "power_on_after_fail");
129 byte = pm_ioread(0x74);
135 pm_iowrite(0x74, byte);
136 printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
138 byte = pm_ioread(0x68);
142 pm_iowrite(0x68, byte);
145 byte = pm_ioread(0x65);
147 pm_iowrite(0x65, byte);
150 byte = pm_ioread(0x55);
152 pm_iowrite(0x55, byte);
154 byte = pm_ioread(0xD7);
155 byte |= 1 << 6 | 1 << 1;;
156 pm_iowrite(0xD7, byte);
159 byte = pm_ioread(0x42);
161 pm_iowrite(0x42, byte);
163 /* Set up NMI on errors */
164 byte = inb(0x70); /* RTC70 */
166 nmi_option = NMI_OFF;
167 get_option(&nmi_option, "nmi");
169 byte &= ~(1 << 7); /* set NMI */
170 printk(BIOS_INFO, "++++++++++set NMI+++++\n");
172 byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */
173 printk(BIOS_INFO, "++++++++++no set NMI+++++\n");
176 if (byte != byte_old) {
180 /*rpr v2.13 2.22 SMBUS PCI Config */
181 byte = pci_read_config8(dev, 0xE1);
182 if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
185 /*Set bit2 to 1, enable Io port 60h read/wrire SMi trapping and
186 *Io port 64h write Smi trapping. conflict with ps2 keyboard
188 //byte |= 1 << 2 | 1 << 3 | 1 << 4;
189 byte |= 1 << 3 | 1 << 4;
190 pci_write_config8(dev, 0xE1, byte);
192 /* 2.5 Enabling Non-Posted Memory Write */
193 axindxc_reg(0x10, 1 << 9, 1 << 9);
195 /* 2.11 IO Trap Settings */
196 abcfg_reg(0x10090, 1 << 16, 1 << 16);
199 pci_write_config32(dev, 0xF0, AB_INDX);
200 /* Initialize the real time clock */
203 /* 4.3 Enabling Upstream DMA Access */
204 axcfg_reg(0x04, 1 << 2, 1 << 2);
205 /* 4.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
206 abcfg_reg(0x10060, 9 << 17, 9 << 17);
207 abcfg_reg(0x10064, 9 << 17, 9 << 17);
209 /* 4.5 Enabling OHCI Prefetch for Performance Enhancement, A12 */
210 abcfg_reg(0x80, 1 << 0, 1<< 0);
212 /* 4.6 B-Link Client's Credit Variable Settings for the Downstream Arbitration Equation */
213 /* 4.7 Enabling Additional Address Bits Checking in Downstream */
214 /* 4.16 IO write and SMI ordering enhancement*/
215 abcfg_reg(0x9c, 3 << 0, 3 << 0);
216 if (REV_SB700_A12 == rev) {
217 abcfg_reg(0x9c, 1 << 8, 1 << 8);
218 } else if (rev >= REV_SB700_A14) {
219 abcfg_reg(0x9c, 1 << 8, 0 << 8);
221 if (REV_SB700_A15 == rev) {
222 abcfg_reg(0x90, 1 << 21, 1 << 21);
223 abcfg_reg(0x9c, 1 << 5 | 1 << 9 | 1 << 15, 1 << 5 | 1 << 9 | 1 << 15);
226 /* 4.8 Set B-Link Prefetch Mode */
227 abcfg_reg(0x80, 3 << 17, 3 << 17);
229 /* 4.9 Enabling Detection of Upstream Interrupts */
230 abcfg_reg(0x94, 1 << 20 | 0x7FFFF, 1 << 20 | 0x00FEE);
232 /* 4.10: Enabling Downstream Posted Transactions to Pass Non-Posted
233 * Transactions for the K8 Platform (for All Revisions) */
234 abcfg_reg(0x10090, 1 << 8, 1 << 8);
236 /* Set ACPI Software clock Throttling Period to 244 us*/
237 byte = pm_ioread(0x68);
239 byte |= (2 << 6); /* 244us */
240 pm_iowrite(0x68, byte);
242 if (REV_SB700_A15 == rev) {
245 /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
246 axindxc_reg(0x02, 1 << 9, 1 << 9);
247 abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
248 abcfg_reg(0x1009C, 0x00000030, 0x00000030);
249 abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
251 /* rpr v2.13 4.19 Enabling Posted Pass Non-Posted Upstream */
252 abcfg_reg(0x58, 0x0000F800, 0x0000E800);
254 /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
255 axindxc_reg(0x02, 1 << 10, 1 << 10);
257 /* rpr v2.13 2.38 Unconditional Shutdown */
258 byte = pci_read_config8(dev, 0x43);
260 pci_write_config8(dev, 0x43, byte);
262 word = pci_read_config16(dev, 0x38);
264 pci_write_config16(dev, 0x38, word);
267 pci_write_config8(dev, 0x43, byte);
269 //ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER
270 byte = pci_read_config8(dev, 0xAE);
272 pci_write_config8(dev, 0xAE, byte);
274 /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
275 /* 4.12: Enabling AB and BIF Clock Gating */
276 abcfg_reg(0x10054, 0xFFFF0000, 0x1040000);
277 abcfg_reg(0x54, 0xFF << 16, 4 << 16);
278 abcfg_reg(0x54, 1 << 24, 0 << 24);
279 abcfg_reg(0x98, 0x0000FF00, 0x00004700);
281 /* 4.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */
282 abcfg_reg(0x10054, 0x0000FFFF, 0x07FF);
284 /* 4.14:Enabling Requester ID for upstream traffic. */
285 abcfg_reg(0x98, 1 << 16, 1 << 16);
287 /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
288 byte = pm2_ioread(0xE5);
290 pm2_iowrite(0xE5, byte);
292 /* Enable IDE controller. */
293 byte = pm_ioread(0x59);
295 pm_iowrite(0x59, byte);
297 printk(BIOS_INFO, "sm_init() end\n");
299 /* Enable NbSb virtual channel */
300 axcfg_reg(0x114, 0x3f << 1, 0 << 1);
301 axcfg_reg(0x120, 0x7f << 1, 0x7f << 1);
302 axcfg_reg(0x120, 7 << 24, 1 << 24);
303 axcfg_reg(0x120, 1 << 31, 1 << 31);
304 abcfg_reg(0x50, 1 << 3, 1 << 3);
307 static int lsmbus_recv_byte(device_t dev)
310 struct resource *res;
313 device = dev->path.i2c.device;
314 pbus = get_pbus_smbus(dev);
316 res = find_resource(pbus->dev, 0x90);
318 return do_smbus_recv_byte(res->base, device);
321 static int lsmbus_send_byte(device_t dev, u8 val)
324 struct resource *res;
327 device = dev->path.i2c.device;
328 pbus = get_pbus_smbus(dev);
330 res = find_resource(pbus->dev, 0x90);
332 return do_smbus_send_byte(res->base, device, val);
335 static int lsmbus_read_byte(device_t dev, u8 address)
338 struct resource *res;
341 device = dev->path.i2c.device;
342 pbus = get_pbus_smbus(dev);
344 res = find_resource(pbus->dev, 0x90);
346 return do_smbus_read_byte(res->base, device, address);
349 static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
352 struct resource *res;
355 device = dev->path.i2c.device;
356 pbus = get_pbus_smbus(dev);
358 res = find_resource(pbus->dev, 0x90);
360 return do_smbus_write_byte(res->base, device, address, val);
363 static struct smbus_bus_operations lops_smbus_bus = {
364 .recv_byte = lsmbus_recv_byte,
365 .send_byte = lsmbus_send_byte,
366 .read_byte = lsmbus_read_byte,
367 .write_byte = lsmbus_write_byte,
370 static void sb700_sm_read_resources(device_t dev)
372 struct resource *res;
374 /* Get the normal pci resources of this device */
375 /* pci_dev_read_resources(dev); */
378 res = new_resource(dev, 0x74);
379 res->base = IO_APIC_ADDR;
380 res->size = 256 * 0x10;
381 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
384 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
387 res = new_resource(dev, 0xB4); /* TODO: test hpet */
388 res->base = 0xfed00000; /* reset hpet to widely accepted address */
390 res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
393 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
395 /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */
398 res = new_resource(dev, 0x90);
401 res->limit = 0xFFFFUL; /* res->base + res->size -1; */
404 res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
406 compact_resources(dev);
409 static void sb700_sm_set_resources(struct device *dev)
411 struct resource *res;
414 pci_dev_set_resources(dev);
415 res = find_resource(dev, 0x74);
416 pci_write_config32(dev, 0x74, res->base | 1 << 3);
418 /* TODO: test hpet */
419 #if 0 //rrg-2.0.3 shows BAR1 not used
420 /* Make SMBUS BAR1(HPET base at offset 14h) visible */
421 byte = pci_read_config8(dev, 0x43);
423 pci_write_config8(dev, 0x43, byte);
426 res = find_resource(dev, 0xB4);
427 /* Program HPET BAR Address */
428 pci_write_config32(dev, 0xB4, res->base);
430 /* Enable decoding of HPET MMIO, enable HPET MSI */
431 byte = pci_read_config8(dev, 0x43);
432 //byte |= (1 << 3); // Make SMBus Bar1 invisible
433 //byte |= ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
435 pci_write_config8(dev, 0x43, byte);
437 /* Enable HPET irq */
438 byte = pci_read_config8(dev, 0x65);
440 pci_write_config8(dev, 0x65, byte);
441 /* TODO: End of test hpet */
443 res = find_resource(dev, 0x90);
444 pci_write_config32(dev, 0x90, res->base | 1);
447 static struct pci_operations lops_pci = {
448 .set_subsystem = pci_dev_set_subsystem,
451 static struct device_operations smbus_ops = {
452 .read_resources = sb700_sm_read_resources,
453 .set_resources = sb700_sm_set_resources,
454 .enable_resources = pci_dev_enable_resources,
456 .scan_bus = scan_static_bus,
457 .ops_pci = &lops_pci,
458 .ops_smbus_bus = &lops_smbus_bus,
461 static const struct pci_driver smbus_driver __pci_driver = {
463 .vendor = PCI_VENDOR_ID_ATI,
464 .device = PCI_DEVICE_ID_ATI_SB700_SM,