2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _SB700_SMBUS_C_
21 #define _SB700_SMBUS_C_
23 #include "sb700_smbus.h"
25 static inline void smbus_delay(void)
27 outb(inb(0x80), 0x80);
30 static int smbus_wait_until_ready(u32 smbus_io_base)
33 loops = SMBUS_TIMEOUT;
36 val = inb(smbus_io_base + SMBHSTSTAT);
38 if (val == 0) { /* ready now */
41 outb(val, smbus_io_base + SMBHSTSTAT);
43 return -2; /* time out */
46 static int smbus_wait_until_done(u32 smbus_io_base)
49 loops = SMBUS_TIMEOUT;
53 val = inb(smbus_io_base + SMBHSTSTAT);
54 val &= 0x1f; /* mask off reserved bits */
56 return -5; /* error */
59 outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
63 return -3; /* timeout */
66 static int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
70 if (smbus_wait_until_ready(smbus_io_base) < 0) {
71 return -2; /* not ready */
74 /* set the device I'm talking too */
75 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
77 byte = inb(smbus_io_base + SMBHSTCTRL);
78 byte &= 0xe3; /* Clear [4:2] */
79 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
80 outb(byte, smbus_io_base + SMBHSTCTRL);
82 /* poll for transaction completion */
83 if (smbus_wait_until_done(smbus_io_base) < 0) {
84 return -3; /* timeout or error */
87 /* read results of transaction */
88 byte = inb(smbus_io_base + SMBHSTCMD);
93 static int do_smbus_send_byte(u32 smbus_io_base, u32 device,
98 if (smbus_wait_until_ready(smbus_io_base) < 0) {
99 return -2; /* not ready */
102 /* set the command... */
103 outb(val, smbus_io_base + SMBHSTCMD);
105 /* set the device I'm talking too */
106 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
108 byte = inb(smbus_io_base + SMBHSTCTRL);
109 byte &= 0xe3; /* Clear [4:2] */
110 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
111 outb(byte, smbus_io_base + SMBHSTCTRL);
113 /* poll for transaction completion */
114 if (smbus_wait_until_done(smbus_io_base) < 0) {
115 return -3; /* timeout or error */
121 int do_smbus_read_byte(u32 smbus_io_base, u32 device,
126 if (smbus_wait_until_ready(smbus_io_base) < 0) {
127 return -2; /* not ready */
130 /* set the command/address... */
131 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
133 /* set the device I'm talking too */
134 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
136 byte = inb(smbus_io_base + SMBHSTCTRL);
137 byte &= 0xe3; /* Clear [4:2] */
138 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
139 outb(byte, smbus_io_base + SMBHSTCTRL);
141 /* poll for transaction completion */
142 if (smbus_wait_until_done(smbus_io_base) < 0) {
143 return -3; /* timeout or error */
146 /* read results of transaction */
147 byte = inb(smbus_io_base + SMBHSTDAT0);
152 int do_smbus_write_byte(u32 smbus_io_base, u32 device,
157 if (smbus_wait_until_ready(smbus_io_base) < 0) {
158 return -2; /* not ready */
161 /* set the command/address... */
162 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
164 /* set the device I'm talking too */
165 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
168 outb(val, smbus_io_base + SMBHSTDAT0);
170 byte = inb(smbus_io_base + SMBHSTCTRL);
171 byte &= 0xe3; /* Clear [4:2] */
172 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
173 outb(byte, smbus_io_base + SMBHSTCTRL);
175 /* poll for transaction completion */
176 if (smbus_wait_until_done(smbus_io_base) < 0) {
177 return -3; /* timeout or error */
183 static void alink_ab_indx(u32 reg_space, u32 reg_addr,
188 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX);
191 * For certain revisions of the chip, the ABCFG registers,
192 * with an address of 0x100NN (where 'N' is any hexadecimal
193 * number), require an extra programming step.*/
194 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
199 /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */
200 outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
202 reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL;
205 /* space = 0: AX_INDXC, AX_DATAC
206 * space = 1: AX_INDXP, AX_DATAP
208 static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
213 /* read axindc to tmp */
214 outl(space << 30 | space << 3 | 0x30, AB_INDX);
215 outl(axindc, AB_DATA);
216 outl(space << 30 | space << 3 | 0x34, AB_INDX);
223 outl(space << 30 | space << 3 | 0x30, AB_INDX);
224 outl(axindc, AB_DATA);
225 outl(space << 30 | space << 3 | 0x34, AB_INDX);