2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
29 static int sata_drive_detect(int portnum, u16 iobar)
33 outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
34 while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
35 (byte != (0xA0 + 0x10 * (portnum % 2))) ||
36 ((byte2 & 0x88) != 0)) {
37 printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
38 if (byte != (0xA0 + 0x10 * (portnum % 2))) {
39 /* This will happen at the first iteration of this loop
40 * if the first SATA port is unpopulated and the
41 * second SATA port is poulated.
43 printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
44 "retrying init\n", i * 10);
47 printk(BIOS_SPEW, "drive detection not yet completed, "
52 printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10);
56 /* This function can be overloaded in mainboard.c */
57 void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev)
59 /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
60 pci_write_config16(dev, 0x86, 0x2c00);
62 /* RPR7.6.2 SATA GENI PHY ports setting */
63 pci_write_config32(dev, 0x88, 0x01B48017);
64 pci_write_config32(dev, 0x8c, 0x01B48019);
65 pci_write_config32(dev, 0x90, 0x01B48016);
66 pci_write_config32(dev, 0x94, 0x01B48016);
67 pci_write_config32(dev, 0x98, 0x01B48016);
68 pci_write_config32(dev, 0x9C, 0x01B48016);
70 /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
71 pci_write_config16(dev, 0xA0, 0xA09A);
72 pci_write_config16(dev, 0xA2, 0xA09F);
73 pci_write_config16(dev, 0xA4, 0xA07A);
74 pci_write_config16(dev, 0xA6, 0xA07A);
75 pci_write_config16(dev, 0xA8, 0xA07A);
76 pci_write_config16(dev, 0xAA, 0xA07A);
79 static void sata_init(struct device *dev)
86 u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
89 struct southbridge_ati_sb700_config *conf;
90 conf = dev->chip_info;
93 /* SATA SMBus Disable */
94 /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
95 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
96 /* Disable SATA SMBUS */
97 byte = pci_read_config8(sm_dev, 0xad);
99 /* Enable SATA and power saving */
100 byte = pci_read_config8(sm_dev, 0xad);
103 pci_write_config8(sm_dev, 0xad, byte);
105 /* RPR 7.2 SATA Initialization */
106 /* Set the interrupt Mapping to INTG# */
107 byte = pci_read_config8(sm_dev, 0xaf);
109 pci_write_config8(sm_dev, 0xaf, byte);
112 rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
114 /* get base address */
115 sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
116 sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
117 sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
118 sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
119 sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
120 sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
122 printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
123 printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */
124 printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */
125 printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */
126 printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
127 printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */
129 /* disable combined mode */
130 byte = pci_read_config8(sm_dev, 0xAD);
132 pci_write_config8(sm_dev, 0xAD, byte);
133 /* Program the 2C to 0x43801002 */
135 pci_write_config32(dev, 0x2c, dword);
138 word = pci_read_config16(dev, 0x04);
140 pci_write_config16(dev, 0x04, word);
142 /* Dynamic power saving */
143 byte = pci_read_config8(dev, 0x40);
145 pci_write_config8(dev, 0x40, byte);
147 /* Set SATA Operation Mode, Set to IDE mode */
148 byte = pci_read_config8(dev, 0x40);
151 pci_write_config8(dev, 0x40, byte);
154 pci_write_config32(dev, 0x8, dword);
156 byte = pci_read_config8(dev, 0x40);
158 pci_write_config8(dev, 0x40, byte);
160 /* Enable the SATA watchdog counter */
161 byte = pci_read_config8(dev, 0x44);
163 pci_write_config8(dev, 0x44, byte);
165 /* Set bit 29 and 24 for A12 */
166 dword = pci_read_config32(dev, 0x40);
167 if (rev_id < 0x14) /* before A12 */
170 dword &= ~(1 << 29); /* A14 and above */
171 pci_write_config32(dev, 0x40, dword);
173 /* set bit 21 for A12 */
174 dword = pci_read_config32(dev, 0x48);
175 if (rev_id < 0x14) /* before A12 */
176 dword |= 1 << 24 | 1 << 21;
178 dword &= ~(1 << 24 | 1 << 21); /* A14 and above */
179 dword &= ~0xFF80; /* 15:7 */
180 dword |= 1 << 15 | 0x7F << 7;
182 pci_write_config32(dev, 0x48, dword);
184 /* Program the watchdog counter to 0x10 */
186 pci_write_config8(dev, 0x46, byte);
187 sb7xx_51xx_setup_sata_phys(dev);
188 /* Enable the I/O, MM, BusMaster access for SATA */
189 byte = pci_read_config8(dev, 0x4);
191 pci_write_config8(dev, 0x4, byte);
193 #if CONFIG_SOUTHBRIDGE_AMD_SP5100
194 /* Master Latency Timer */
195 pci_write_config32(dev, 0xC, 0x00004000);
198 /* RPR7.7 SATA drive detection. */
199 /* Use BAR5+0x128,BAR0 for Primary Slave */
200 /* Use BAR5+0x1A8,BAR0 for Primary Slave */
201 /* Use BAR5+0x228,BAR2 for Secondary Master */
202 /* Use BAR5+0x2A8,BAR2 for Secondary Slave */
203 /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
204 /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
206 /* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
208 for (i = 0; i < 4; i++) {
209 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
210 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
213 /* If the drive status is 0x1 then we see it but we aren't talking to it. */
214 /* Try to do something about it. */
215 printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
217 /* Read in Port-N Serial ATA Control Register */
218 byte = read8(sata_bar5 + 0x12C + 0x80 * i);
220 /* Set Reset Bit and 1.5g bit */
222 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
227 /* Clear Reset Bit */
229 write8((sata_bar5 + 0x12C + 0x80 * i), byte);
235 byte = read8(sata_bar5 + 0x128 + 0x80 * i);
236 printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
241 for (j = 0; j < 10; j++) {
242 if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
245 printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
246 (i / 2) ? "Secondary" : "Primary",
247 (i % 2 ) ? "Slave" : "Master",
248 (j == 10) ? "not " : "",
249 (j == 10) ? j : j + 1);
251 printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
252 (i / 2) ? "Secondary" : "Primary",
253 (i % 2 ) ? "Slave" : "Master", i);
257 /* Below is CIM InitSataLateFar */
258 /* Enable interrupts from the HBA */
259 byte = read8(sata_bar5 + 0x4);
261 write8((sata_bar5 + 0x4), byte);
263 /* Clear error status */
264 write32((sata_bar5 + 0x130), 0xFFFFFFFF);
265 write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
266 write32((sata_bar5 + 0x230), 0xFFFFFFFF);
267 write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
268 write32((sata_bar5 + 0x330), 0xFFFFFFFF);
269 write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
271 /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
272 /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
275 /* word = pm_ioread(0x28); */
276 /* byte = pm_ioread(0x29); */
277 /* word |= byte<<8; */
278 /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */
279 /* write32(word, 0x80000000); */
282 static struct pci_operations lops_pci = {
283 /* .set_subsystem = pci_dev_set_subsystem, */
286 static struct device_operations sata_ops = {
287 .read_resources = pci_dev_read_resources,
288 .set_resources = pci_dev_set_resources,
289 .enable_resources = pci_dev_enable_resources,
292 .ops_pci = &lops_pci,
295 static const struct pci_driver sata0_driver __pci_driver = {
297 .vendor = PCI_VENDOR_ID_ATI,
298 .device = PCI_DEVICE_ID_ATI_SB700_SATA,