Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial...
[coreboot.git] / src / southbridge / amd / sb700 / lpc.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18  */
19
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
28 #include <bitops.h>
29 #include <arch/io.h>
30 #include <arch/ioapic.h>
31 #include <cbmem.h>
32 #include "sb700.h"
33
34 static void lpc_init(device_t dev)
35 {
36         u8 byte;
37         u32 dword;
38         device_t sm_dev;
39
40         /* Enable the LPC Controller */
41         sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
42         dword = pci_read_config32(sm_dev, 0x64);
43         dword |= 1 << 20;
44         pci_write_config32(sm_dev, 0x64, dword);
45
46         /* Initialize isa dma */
47 #if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
48         printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
49 #else
50         isa_dma_init();
51 #endif
52
53         /* Enable DMA transaction on the LPC bus */
54         byte = pci_read_config8(dev, 0x40);
55         byte |= (1 << 2);
56         pci_write_config8(dev, 0x40, byte);
57
58         /* Disable the timeout mechanism on LPC */
59         byte = pci_read_config8(dev, 0x48);
60         byte &= ~(1 << 7);
61         pci_write_config8(dev, 0x48, byte);
62
63         /* Disable LPC MSI Capability */
64         byte = pci_read_config8(dev, 0x78);
65         byte &= ~(1 << 1);
66         pci_write_config8(dev, 0x78, byte);
67
68         /* hack, but the whole sb700 startup lacks any device which
69            is doing the acpi init */
70 #if CONFIG_HAVE_ACPI_RESUME == 1
71         {
72         extern u8 acpi_slp_type;
73         u16 tmp = inw(ACPI_PM1_CNT_BLK);
74         acpi_slp_type = ((tmp & (7 << 10)) >> 10);
75         printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
76         }
77 #endif
78 }
79
80 void set_cbmem_toc(struct cbmem_entry *toc)
81 {
82         u32 dword = (u32) toc;
83         int nvram_pos = 0xfc, i;
84         for (i = 0; i<4; i++) {
85                 outb(nvram_pos, BIOSRAM_INDEX);
86                 outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
87                 nvram_pos++;
88         }
89 }
90
91 static void sb700_lpc_read_resources(device_t dev)
92 {
93         struct resource *res;
94
95         /* Get the normal pci resources of this device */
96         pci_dev_read_resources(dev);    /* We got one for APIC, or one more for TRAP */
97
98         pci_get_resource(dev, 0xA0); /* SPI ROM base address */
99
100         /* Add an extra subtractive resource for both memory and I/O. */
101         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
102         res->base = 0;
103         res->size = 0x1000;
104         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
105                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
106
107         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
108         res->base = 0xff800000;
109         res->size = 0x00800000; /* 8 MB for flash */
110         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
111                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
112
113         res = new_resource(dev, 3); /* IOAPIC */
114         res->base = IO_APIC_ADDR;
115         res->size = 0x00001000;
116         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
117
118         compact_resources(dev);
119 }
120
121 static void sb700_lpc_set_resources(struct device *dev)
122 {
123         struct resource *res;
124
125         pci_dev_set_resources(dev);
126
127         /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
128         res = find_resource(dev, 0xA0);
129         pci_write_config32(dev, 0xA0, res->base | 1 << 1);
130 }
131
132 /**
133  * @brief Enable resources for children devices
134  *
135  * @param dev the device whose children's resources are to be enabled
136  *
137  */
138 static void sb700_lpc_enable_childrens_resources(device_t dev)
139 {
140         struct bus *link;
141         u32 reg, reg_x;
142         int var_num = 0;
143         u16 reg_var[3] = {0x0, 0x0, 0x0};
144         u8 wiosize = pci_read_config8(dev, 0x74);
145
146         reg = pci_read_config32(dev, 0x44);
147         reg_x = pci_read_config32(dev, 0x48);
148
149         for (link = dev->link_list; link; link = link->next) {
150                 device_t child;
151                 for (child = link->children; child;
152                      child = child->sibling) {
153                         if (child->enabled
154                             && (child->path.type == DEVICE_PATH_PNP)) {
155                                 struct resource *res;
156                                 for (res = child->resource_list; res; res = res->next) {
157                                         u32 base, end;  /*  don't need long long */
158                                         if (!(res->flags & IORESOURCE_IO))
159                                                 continue;
160                                         base = res->base;
161                                         end = resource_end(res);
162                                         printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
163                                              dev_path(child), base, end);
164                                         switch (base) {
165                                         case 0x60:      /*  KB */
166                                         case 0x64:      /*  MS */
167                                                 reg |= (1 << 29);
168                                                 break;
169                                         case 0x3f8:     /*  COM1 */
170                                                 reg |= (1 << 6);
171                                                 break;
172                                         case 0x2f8:     /*  COM2 */
173                                                 reg |= (1 << 7);
174                                                 break;
175                                         case 0x378:     /*  Parallel 1 */
176                                                 reg |= (1 << 0);
177                                                 reg |= (1 << 1); /* + 0x778 for ECP */
178                                                 break;
179                                         case 0x3f0:     /*  FD0 */
180                                                 reg |= (1 << 26);
181                                                 break;
182                                         case 0x220:     /*  Audio 0 */
183                                                 reg |= (1 << 8);
184                                                 break;
185                                         case 0x300:     /*  Midi 0 */
186                                                 reg |= (1 << 18);
187                                                 break;
188                                         case 0x400:
189                                                 reg_x |= (1 << 16);
190                                                 break;
191                                         case 0x480:
192                                                 reg_x |= (1 << 17);
193                                                 break;
194                                         case 0x500:
195                                                 reg_x |= (1 << 18);
196                                                 break;
197                                         case 0x580:
198                                                 reg_x |= (1 << 19);
199                                                 break;
200                                         case 0x4700:
201                                                 reg_x |= (1 << 22);
202                                                 break;
203                                         case 0xfd60:
204                                                 reg_x |= (1 << 23);
205                                                 break;
206                                         default:
207                                                 if (var_num >= 3)
208                                                         continue;       /* only 3 var ; compact them ? */
209                                                 switch (var_num) {
210                                                 case 0:
211                                                         reg_x |= (1 << 2);
212                                                         if ((end - base) < 16)
213                                                                 wiosize |= (1 << 0);
214                                                         break;
215                                                 case 1:
216                                                         reg_x |= (1 << 24);
217                                                         if ((end - base) < 16)
218                                                                 wiosize |= (1 << 2);
219                                                         break;
220                                                 case 2:
221                                                         reg_x |= (1 << 25);
222                                                         reg_x |= (1 << 24);
223                                                         if ((end - base) < 16)
224                                                                 wiosize |= (1 << 3);
225                                                         break;
226                                                 }
227                                                 reg_var[var_num++] =
228                                                     base & 0xffff;
229                                         }
230                                 }
231                         }
232                 }
233         }
234         pci_write_config32(dev, 0x44, reg);
235         pci_write_config32(dev, 0x48, reg_x);
236         /* Set WideIO for as many IOs found (fall through is on purpose) */
237         switch (var_num) {
238         case 2:
239                 pci_write_config16(dev, 0x90, reg_var[2]);
240         case 1:
241                 pci_write_config16(dev, 0x66, reg_var[1]);
242         case 0:
243                 pci_write_config16(dev, 0x64, reg_var[0]);
244                 break;
245         }
246         pci_write_config8(dev, 0x74, wiosize);
247 }
248
249 static void sb700_lpc_enable_resources(device_t dev)
250 {
251         pci_dev_enable_resources(dev);
252         sb700_lpc_enable_childrens_resources(dev);
253 }
254
255 static struct pci_operations lops_pci = {
256         .set_subsystem = pci_dev_set_subsystem,
257 };
258
259 static struct device_operations lpc_ops = {
260         .read_resources = sb700_lpc_read_resources,
261         .set_resources = sb700_lpc_set_resources,
262         .enable_resources = sb700_lpc_enable_resources,
263         .init = lpc_init,
264         .scan_bus = scan_static_bus,
265         .ops_pci = &lops_pci,
266 };
267 static const struct pci_driver lpc_driver __pci_driver = {
268         .ops = &lpc_ops,
269         .vendor = PCI_VENDOR_ID_ATI,
270         .device = PCI_DEVICE_ID_ATI_SB700_LPC,
271 };