2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pnp.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
26 #include <pc80/mc146818rtc.h>
27 #include <pc80/isa-dma.h>
30 #include <arch/ioapic.h>
34 static void lpc_init(device_t dev)
40 /* Enable the LPC Controller */
41 sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
42 dword = pci_read_config32(sm_dev, 0x64);
44 pci_write_config32(sm_dev, 0x64, dword);
46 /* Initialize isa dma */
47 #if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
48 printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
53 /* Enable DMA transaction on the LPC bus */
54 byte = pci_read_config8(dev, 0x40);
56 pci_write_config8(dev, 0x40, byte);
58 /* Disable the timeout mechanism on LPC */
59 byte = pci_read_config8(dev, 0x48);
61 pci_write_config8(dev, 0x48, byte);
63 /* Disable LPC MSI Capability */
64 byte = pci_read_config8(dev, 0x78);
66 pci_write_config8(dev, 0x78, byte);
68 /* hack, but the whole sb700 startup lacks any device which
69 is doing the acpi init */
70 #if CONFIG_HAVE_ACPI_RESUME == 1
72 extern u8 acpi_slp_type;
73 u16 tmp = inw(ACPI_PM1_CNT_BLK);
74 acpi_slp_type = ((tmp & (7 << 10)) >> 10);
75 printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
80 void set_cbmem_toc(struct cbmem_entry *toc)
82 u32 dword = (u32) toc;
83 int nvram_pos = 0xfc, i;
84 for (i = 0; i<4; i++) {
85 outb(nvram_pos, BIOSRAM_INDEX);
86 outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
91 static void sb700_lpc_read_resources(device_t dev)
95 /* Get the normal pci resources of this device */
96 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
98 pci_get_resource(dev, 0xA0); /* SPI ROM base address */
100 /* Add an extra subtractive resource for both memory and I/O. */
101 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
104 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
105 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
107 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
108 res->base = 0xff800000;
109 res->size = 0x00800000; /* 8 MB for flash */
110 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
111 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
113 res = new_resource(dev, 3); /* IOAPIC */
114 res->base = IO_APIC_ADDR;
115 res->size = 0x00001000;
116 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
118 compact_resources(dev);
121 static void sb700_lpc_set_resources(struct device *dev)
123 struct resource *res;
125 pci_dev_set_resources(dev);
127 /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
128 res = find_resource(dev, 0xA0);
129 pci_write_config32(dev, 0xA0, res->base | 1 << 1);
133 * @brief Enable resources for children devices
135 * @param dev the device whose children's resources are to be enabled
138 static void sb700_lpc_enable_childrens_resources(device_t dev)
145 reg = pci_read_config32(dev, 0x44);
146 reg_x = pci_read_config32(dev, 0x48);
148 for (link = dev->link_list; link; link = link->next) {
150 for (child = link->children; child;
151 child = child->sibling) {
153 && (child->path.type == DEVICE_PATH_PNP)) {
154 struct resource *res;
155 for (res = child->resource_list; res; res = res->next) {
156 u32 base, end; /* don't need long long */
157 if (!(res->flags & IORESOURCE_IO))
160 end = resource_end(res);
161 printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
162 dev_path(child), base, end);
168 case 0x3f8: /* COM1 */
171 case 0x2f8: /* COM2 */
174 case 0x378: /* Parallal 1 */
177 case 0x3f0: /* FD0 */
180 case 0x220: /* Aduio 0 */
183 case 0x300: /* Midi 0 */
206 continue; /* only 3 var ; compact them ? */
225 pci_write_config32(dev, 0x44, reg);
226 pci_write_config32(dev, 0x48, reg_x);
227 /* Set WideIO for as many IOs found (fall through is on purpose) */
230 pci_write_config16(dev, 0x90, reg_var[2]);
232 pci_write_config16(dev, 0x66, reg_var[1]);
234 pci_write_config16(dev, 0x64, reg_var[0]);
239 static void sb700_lpc_enable_resources(device_t dev)
241 pci_dev_enable_resources(dev);
242 sb700_lpc_enable_childrens_resources(dev);
245 static struct pci_operations lops_pci = {
246 .set_subsystem = pci_dev_set_subsystem,
249 static struct device_operations lpc_ops = {
250 .read_resources = sb700_lpc_read_resources,
251 .set_resources = sb700_lpc_set_resources,
252 .enable_resources = sb700_lpc_enable_resources,
254 .scan_bus = scan_static_bus,
255 .ops_pci = &lops_pci,
257 static const struct pci_driver lpc_driver __pci_driver = {
259 .vendor = PCI_VENDOR_ID_ATI,
260 .device = PCI_DEVICE_ID_ATI_SB700_LPC,