2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <arch/romcc_io.h>
23 #include <device/pci_ids.h>
26 * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
28 * Hardware should enable LPC ROM by pin straps. This function does not
29 * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
31 * The SB600 power-on default is to map 256K ROM space.
33 * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15.
35 static void sb600_enable_rom(void)
40 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI,
41 PCI_DEVICE_ID_ATI_SB600_LPC), 0);
43 /* Decode variable LPC ROM address ranges 1 and 2. */
44 reg8 = pci_read_config8(dev, 0x48);
45 reg8 |= (1 << 3) | (1 << 4);
46 pci_write_config8(dev, 0x48, reg8);
48 /* LPC ROM address range 1: */
49 /* Enable LPC ROM range mirroring start at 0x000e(0000). */
50 pci_write_config16(dev, 0x68, 0x000e);
51 /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
52 pci_write_config16(dev, 0x6a, 0x000f);
54 /* LPC ROM address range 2: */
56 * Enable LPC ROM range start at:
62 pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */
63 /* Enable LPC ROM range end at 0xffff(ffff). */
64 pci_write_config16(dev, 0x6e, 0xffff);