2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #define SMBUS_ERROR -1
22 #define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
23 #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
27 #define SMB_CTRL_STS 0x02
28 #define SMB_CTRL1 0x03
30 #define SMB_CTRL2 0x05
31 #define SMB_CTRL3 0x06
33 #define SMB_STS_SLVSTP (0x01 << 7)
34 #define SMB_STS_SDAST (0x01 << 6)
35 #define SMB_STS_BER (0x01 << 5)
36 #define SMB_STS_NEGACK (0x01 << 4)
37 #define SMB_STS_STASTR (0x01 << 3)
38 #define SMB_STS_NMATCH (0x01 << 2)
39 #define SMB_STS_MASTER (0x01 << 1)
40 #define SMB_STS_XMIT (0x01 << 0)
42 #define SMB_CSTS_TGSCL (0x01 << 5)
43 #define SMB_CSTS_TSDA (0x01 << 4)
44 #define SMB_CSTS_GCMTCH (0x01 << 3)
45 #define SMB_CSTS_MATCH (0x01 << 2)
46 #define SMB_CSTS_BB (0x01 << 1)
47 #define SMB_CSTS_BUSY (0x01 << 0)
49 #define SMB_CTRL1_STASTRE (0x01 << 7)
50 #define SMB_CTRL1_NMINTE (0x01 << 6)
51 #define SMB_CTRL1_GCMEN (0x01 << 5)
52 #define SMB_CTRL1_ACK (0x01 << 4)
53 #define SMB_CTRL1_RSVD (0x01 << 3)
54 #define SMB_CTRL1_INTEN (0x01 << 2)
55 #define SMB_CTRL1_STOP (0x01 << 1)
56 #define SMB_CTRL1_START (0x01 << 0)
58 #define SMB_ADD_SAEN (0x01 << 7)
60 #define SMB_CTRL2_ENABLE 0x01
62 #define SMBUS_TIMEOUT (100*1000*10)
63 #define SMBUS_STATUS_MASK 0xfbff
65 static void smbus_delay(void)
70 static int smbus_wait(unsigned smbus_io_base)
72 unsigned long loops = SMBUS_TIMEOUT;
77 val = inb(smbus_io_base + SMB_STS);
78 if ((val & SMB_STS_SDAST) != 0)
80 if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
81 printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val);
86 outb(0, smbus_io_base + SMB_STS);
87 return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
90 static int smbus_write(unsigned smbus_io_base, unsigned char byte)
93 outb(byte, smbus_io_base + SMB_SDA);
94 return smbus_wait(smbus_io_base);
97 /* generate a smbus start condition */
98 static int smbus_start_condition(unsigned smbus_io_base)
102 /* issue a START condition */
103 val = inb(smbus_io_base + SMB_CTRL1);
104 outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
106 /* check for bus conflict */
107 val = inb(smbus_io_base + SMB_STS);
108 if ((val & SMB_STS_BER) != 0)
111 return smbus_wait(smbus_io_base);
114 static int smbus_check_stop_condition(unsigned smbus_io_base)
118 loops = SMBUS_TIMEOUT;
119 /* check for SDA status */
122 val = inb(smbus_io_base + SMB_CTRL1);
123 if ((val & SMB_CTRL1_STOP) == 0) {
127 return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
129 /* Make sure everything is cleared and ready to go */
131 val = inb(smbus_io_base + SMB_CTRL1);
132 outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE),
133 smbus_io_base + SMB_CTRL1);
135 outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR,
136 smbus_io_base + SMB_STS);
138 val = inb(smbus_io_base + SMB_CTRL_STS);
139 outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS);
142 static int smbus_stop_condition(unsigned smbus_io_base)
145 val = inb(smbus_io_base + SMB_CTRL1);
146 outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
151 static int smbus_ack(unsigned smbus_io_base, int state)
153 unsigned char val = inb(smbus_io_base + SMB_CTRL1);
156 outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
158 outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
163 static int smbus_send_slave_address(unsigned smbus_io_base,
164 unsigned char device)
168 /* send the slave address */
169 outb(device, smbus_io_base + SMB_SDA);
171 /* check for bus conflict and NACK */
172 val = inb(smbus_io_base + SMB_STS);
173 if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
174 printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val);
177 return smbus_wait(smbus_io_base);
180 static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
184 /* send the command */
185 outb(command, smbus_io_base + SMB_SDA);
187 /* check for bus conflict and NACK */
188 val = inb(smbus_io_base + SMB_STS);
189 if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
192 return smbus_wait(smbus_io_base);
195 static void _doread(unsigned smbus_io_base, unsigned char device,
196 unsigned char address, unsigned char *data, int count)
202 if ((ret = smbus_check_stop_condition(smbus_io_base)))
207 if ((ret = smbus_start_condition(smbus_io_base)))
211 if ((ret = smbus_send_slave_address(smbus_io_base, device)))
215 if ((ret = smbus_send_command(smbus_io_base, address)))
219 if ((ret = smbus_start_condition(smbus_io_base)))
222 /* Clear the ack for multiple byte reads */
223 smbus_ack(smbus_io_base, (count == 1) ? 1 : 0);
226 if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01)))
230 /* Set the ACK if this is the next to last byte */
231 smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
233 /* Set the stop bit if this is the last byte to read */
236 smbus_stop_condition(smbus_io_base);
238 val = inb(smbus_io_base + SMB_SDA);
242 ret = smbus_wait(smbus_io_base);
253 printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret);
256 static inline unsigned char do_smbus_read_byte(unsigned smbus_io_base,
257 unsigned char device, unsigned char address)
259 unsigned char val = 0;
260 _doread(smbus_io_base, device, address, &val, sizeof(val));
264 static inline unsigned short do_smbus_read_word(unsigned smbus_io_base,
265 unsigned char device, unsigned char address)
267 unsigned short val = 0;
268 _doread(smbus_io_base, device, address, (unsigned char *)&val,
273 static int _dowrite(unsigned smbus_io_base, unsigned char device,
274 unsigned char address, unsigned char *data, int count)
279 if ((ret = smbus_check_stop_condition(smbus_io_base)))
282 if ((ret = smbus_start_condition(smbus_io_base)))
285 if ((ret = smbus_send_slave_address(smbus_io_base, device)))
288 if ((ret = smbus_send_command(smbus_io_base, address)))
292 if ((ret = smbus_write(smbus_io_base, *data++)))
297 smbus_stop_condition(smbus_io_base);
301 printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret);
305 static inline int do_smbus_write_byte(unsigned smbus_io_base,
306 unsigned char device, unsigned char address, unsigned char data)
308 return _dowrite(smbus_io_base, device, address,
309 (unsigned char *)&data, 1);
312 static inline int do_smbus_write_word(unsigned smbus_io_base,
313 unsigned char device, unsigned char address, unsigned short data)
315 return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,