2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #define Cx5536_ID ( 0x208F1022)
25 /* SouthBridge Equates */
26 #define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
27 #define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
28 #define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
29 #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
31 #define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
32 #define SMBUS_IO_BASE 0x6000
33 #define GPIO_IO_BASE 0x6100
34 #define MFGPT_IO_BASE 0x6200
35 #define ACPI_IO_BASE 0x9C00
36 #define PMS_IO_BASE 0x9D00
38 #define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
39 #define CHIPSET_DEV_NUM 15
40 #define IDSEL_BASE 11 // bit 11 = device 1
42 /* Cs5536 as follows. */
46 /* port2 - USB Controller #2 */
47 /* port3 - ATA-5 Controller */
50 /* port6 - USB Controller #1 */
53 #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
54 #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
55 #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
56 #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
57 #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
58 #define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
59 #define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
60 #define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
65 #define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00)
66 #define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01)
67 #define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
72 #define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00)
73 #define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
74 #define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
79 #define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)
80 #define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
81 #define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
82 #define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
83 #define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05)
84 #define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08)
85 #define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09)
86 #define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A)
87 #define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
92 #define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00)
93 #define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
94 #define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
95 #define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
100 #define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00)
101 #define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
102 #define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
107 #define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00)
108 #define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01)
109 #define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
110 #define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
111 #define GLPCI_CRTL_PPIDE_SET (1 << 17)
115 #define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00)
116 #define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01)
117 #define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
118 #define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10)
123 #define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00)
124 #define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
125 #define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
126 #define LBAR_EN (0x01)
127 #define IO_MASK (0x1f)
128 #define MEM_MASK (0x0FFFFF)
129 #define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08)
130 #define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09)
131 #define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A)
132 #define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
133 #define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
134 #define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
135 #define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
136 #define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
138 #define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010)
139 #define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011)
140 #define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012)
141 #define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013)
142 #define MDD_LEG_IO (MSR_SB_MDD + 0x014)
143 #define MDD_PIN_OPT (MSR_SB_MDD + 0x015)
144 #define MDD_SOFT_IRQ (MSR_SB_MDD + 0x016)
145 #define MDD_SOFT_RESET (MSR_SB_MDD + 0x017)
146 #define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018)
147 #define MDD_NORF_T01 (MSR_SB_MDD + 0x019)
148 #define MDD_NORF_T23 (MSR_SB_MDD + 0x01A)
149 #define MDD_NANDF_DATA (MSR_SB_MDD + 0x01B)
150 #define MDD_NADF_CNTL (MSR_SB_MDD + 0x01C)
151 #define MDD_AC_DMA (MSR_SB_MDD + 0x01E)
152 #define MDD_KEL_CNTRL (MSR_SB_MDD + 0x01F)
154 #define MDD_IRQM_YLOW (MSR_SB_MDD + 0x020)
155 #define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x021)
156 #define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x022)
157 #define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x023)
158 #define MDD_IRQM_PRIM (MSR_SB_MDD + 0x024)
159 #define MDD_IRQM_LPC (MSR_SB_MDD + 0x025)
160 #define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x026)
161 #define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x027)
163 #define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x028)
164 #define MDD_MFGPT_NR (MSR_SB_MDD + 0x029)
165 #define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x02A)
166 #define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x02B)
168 #define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x030)
169 #define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x031)
170 #define MDD_FLOP_S372 (MSR_SB_MDD + 0x032)
171 #define MDD_FLOP_S377 (MSR_SB_MDD + 0x033)
173 #define MDD_PIC_S (MSR_SB_MDD + 0x034)
174 #define MDD_PIT_S (MSR_SB_MDD + 0x036)
175 #define MDD_PIT_CNTRL (MSR_SB_MDD + 0x037)
177 #define MDD_UART1_MOD (MSR_SB_MDD + 0x038)
178 #define MDD_UART1_DON (MSR_SB_MDD + 0x039)
179 #define MDD_UART1_CONF (MSR_SB_MDD + 0x03A)
180 #define MDD_UART2_MOD (MSR_SB_MDD + 0x03C)
181 #define MDD_UART2_DON (MSR_SB_MDD + 0x03D)
182 #define MDD_UART2_CONF (MSR_SB_MDD + 0x03E)
184 #define MDD_DMA_MAP (MSR_SB_MDD + 0x040)
185 #define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x041)
186 #define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x042)
187 #define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x043)
188 #define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x044)
189 #define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x045)
190 #define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x046)
191 #define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x047)
192 #define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x048)
193 #define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x049)
195 #define MDD_LPC_EADDR (MSR_SB_MDD + 0x04C)
196 #define MDD_LPC_ESTAT (MSR_SB_MDD + 0x04D)
197 #define MDD_LPC_SIRQ (MSR_SB_MDD + 0x04E)
198 #define MDD_LPC_RES (MSR_SB_MDD + 0x04F)
200 #define MDD_PML_TMR (MSR_SB_MDD + 0x050)
201 #define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x054)
202 #define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x055)
203 #define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x056)
204 #define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x057)
207 /* ***********************************************************/
208 /* LBUS Device Equates - */
209 /* ***********************************************************/
217 #define SMB_STS_SLVSTP (0x01 << 7)
218 #define SMB_STS_SDAST (0x01 << 6)
219 #define SMB_STS_BER (0x01 << 5)
220 #define SMB_STS_NEGACK (0x01 << 4)
221 #define SMB_STS_STASTR (0x01 << 3)
222 #define SMB_STS_NMATCH (0x01 << 2)
223 #define SMB_STS_MASTER (0x01 << 1)
224 #define SMB_STS_XMIT (0x01 << 0)
226 #define SMB_CTRL_STS 0x02
227 #define SMB_CSTS_TGSCL (0x01 << 5)
228 #define SMB_CSTS_TSDA (0x01 << 4)
229 #define SMB_CSTS_GCMTCH (0x01 << 3)
230 #define SMB_CSTS_MATCH (0x01 << 2)
231 #define SMB_CSTS_BB (0x01 << 1)
232 #define SMB_CSTS_BUSY (0x01 << 0)
234 #define SMB_CTRL1 0x03
235 #define SMB_CTRL1_STASTRE (0x01 << 7)
236 #define SMB_CTRL1_NMINTE (0x01 << 6)
237 #define SMB_CTRL1_GCMEN (0x01 << 5)
238 #define SMB_CTRL1_ACK (0x01 << 4)
239 #define SMB_CTRL1_RSVD (0x01 << 3)
240 #define SMB_CTRL1_INTEN (0x01 << 2)
241 #define SMB_CTRL1_STOP (0x01 << 1)
242 #define SMB_CTRL1_START (0x01 << 0)
245 #define SMB_ADD_SAEN (0x01 << 7)
247 #define SMB_CTRL2 0x05
248 #define SMB_CTRL2_ENABLE (0x01 << 0)
250 #define SMB_CTRL3 0x06
256 #define GPIOL_0_SET (1 << 0)
257 #define GPIOL_1_SET (1 << 1)
258 #define GPIOL_2_SET (1 << 2)
259 #define GPIOL_3_SET (1 << 3)
260 #define GPIOL_4_SET (1 << 4)
261 #define GPIOL_5_SET (1 << 5)
262 #define GPIOL_6_SET (1 << 6)
263 #define GPIOL_7_SET (1 << 7)
264 #define GPIOL_8_SET (1 << 8)
265 #define GPIOL_9_SET (1 << 9)
266 #define GPIOL_10_SET (1 << 10)
267 #define GPIOL_11_SET (1 << 11)
268 #define GPIOL_12_SET (1 << 12)
269 #define GPIOL_13_SET (1 << 13)
270 #define GPIOL_14_SET (1 << 14)
271 #define GPIOL_15_SET (1 << 15)
273 #define GPIOL_0_CLEAR (1 << 16)
274 #define GPIOL_1_CLEAR (1 << 17)
275 #define GPIOL_2_CLEAR (1 << 18)
276 #define GPIOL_3_CLEAR (1 << 19)
277 #define GPIOL_4_CLEAR (1 << 20)
278 #define GPIOL_5_CLEAR (1 << 21)
279 #define GPIOL_6_CLEAR (1 << 22)
280 #define GPIOL_7_CLEAR (1 << 23)
281 #define GPIOL_8_CLEAR (1 << 24)
282 #define GPIOL_9_CLEAR (1 << 25)
283 #define GPIOL_10_CLEAR (1 << 26)
284 #define GPIOL_11_CLEAR (1 << 27)
285 #define GPIOL_12_CLEAR (1 << 28)
286 #define GPIOL_13_CLEAR (1 << 29)
287 #define GPIOL_14_CLEAR (1 << 30)
288 #define GPIOL_15_CLEAR (1 << 31)
290 #define GPIOH_16_SET (1 << 0)
291 #define GPIOH_17_SET (1 << 1)
292 #define GPIOH_18_SET (1 << 2)
293 #define GPIOH_19_SET (1 << 3)
294 #define GPIOH_20_SET (1 << 4)
295 #define GPIOH_21_SET (1 << 5)
296 #define GPIOH_22_SET (1 << 6)
297 #define GPIOH_23_SET (1 << 7)
298 #define GPIOH_24_SET (1 << 8)
299 #define GPIOH_25_SET (1 << 9)
300 #define GPIOH_26_SET (1 << 10)
301 #define GPIOH_27_SET (1 << 11)
302 #define GPIOH_28_SET (1 << 12)
303 #define GPIOH_29_SET (1 << 13)
304 #define GPIOH_30_SET (1 << 14)
305 #define GPIOH_31_SET (1 << 15)
307 #define GPIOH_16_CLEAR (1 << 16)
308 #define GPIOH_17_CLEAR (1 << 17)
309 #define GPIOH_18_CLEAR (1 << 18)
310 #define GPIOH_19_CLEAR (1 << 19)
311 #define GPIOH_20_CLEAR (1 << 20)
312 #define GPIOH_21_CLEAR (1 << 21)
313 #define GPIOH_22_CLEAR (1 << 22)
314 #define GPIOH_23_CLEAR (1 << 23)
315 #define GPIOH_24_CLEAR (1 << 24)
316 #define GPIOH_25_CLEAR (1 << 25)
317 #define GPIOH_26_CLEAR (1 << 26)
318 #define GPIOH_27_CLEAR (1 << 27)
319 #define GPIOH_28_CLEAR (1 << 28)
320 #define GPIOH_29_CLEAR (1 << 29)
321 #define GPIOH_30_CLEAR (1 << 30)
322 #define GPIOH_31_CLEAR (1 << 31)
325 /* GPIO LOW Bank Bit Registers*/
326 #define GPIOL_OUTPUT_VALUE (0x00)
327 #define GPIOL_OUTPUT_ENABLE (0x04)
328 #define GPIOL_OUT_OPENDRAIN (0x08)
329 #define GPIOL_OUTPUT_INVERT_ENABLE (0x0C)
330 #define GPIOL_OUT_AUX1_SELECT (0x10)
331 #define GPIOL_OUT_AUX2_SELECT (0x14)
332 #define GPIOL_PULLUP_ENABLE (0x18)
333 #define GPIOL_PULLDOWN_ENABLE (0x1C)
334 #define GPIOL_INPUT_ENABLE (0x20)
335 #define GPIOL_INPUT_INVERT_ENABLE (0x24)
336 #define GPIOL_IN_FILTER_ENABLE (0x28)
337 #define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C)
338 #define GPIOL_READ_BACK (0x30)
339 #define GPIOL_IN_AUX1_SELECT (0x34)
340 #define GPIOL_EVENTS_ENABLE (0x38)
341 #define GPIOL_LOCK_ENABLE (0x3C)
342 #define GPIOL_IN_POSEDGE_ENABLE (0x40)
343 #define GPIOL_IN_NEGEDGE_ENABLE (0x44)
344 #define GPIOL_IN_POSEDGE_STATUS (0x48)
345 #define GPIOL_IN_NEGEDGE_STATUS (0x4C)
347 /* GPIO High Bank Bit Registers*/
348 #define GPIOH_OUTPUT_VALUE (0x80)
349 #define GPIOH_OUTPUT_ENABLE (0x84)
350 #define GPIOH_OUT_OPENDRAIN (0x88)
351 #define GPIOH_OUTPUT_INVERT_ENABLE (0x8C)
352 #define GPIOH_OUT_AUX1_SELECT (0x90)
353 #define GPIOH_OUT_AUX2_SELECT (0x94)
354 #define GPIOH_PULLUP_ENABLE (0x98)
355 #define GPIOH_PULLDOWN_ENABLE (0x9C)
356 #define GPIOH_INPUT_ENABLE (0x0A0)
357 #define GPIOH_INPUT_INVERT_ENABLE (0x0A4)
358 #define GPIOH_IN_FILTER_ENABLE (0x0A8)
359 #define GPIOH_IN_EVENTCOUNT_ENABLE (0x0AC)
360 #define GPIOH_READ_BACK (0x0B0)
361 #define GPIOH_IN_AUX1_SELECT (0x0B4)
362 #define GPIOH_EVENTS_ENABLE (0x0B8)
363 #define GPIOH_LOCK_ENABLE (0x0BC)
364 #define GPIOH_IN_POSEDGE_ENABLE (0x0C0)
365 #define GPIOH_IN_NEGEDGE_ENABLE (0x0C4)
366 #define GPIOH_IN_POSEDGE_STATUS (0x0C8)
367 #define GPIOH_IN_NEGEDGE_STATUS (0x0CC)
369 /* Input Conditioning Function Registers*/
370 #define GPIO_00_FILTER_AMOUNT (0x50)
371 #define GPIO_00_FILTER_COUNT (0x52)
372 #define GPIO_00_EVENT_COUNT (0x54)
373 #define GPIO_00_EVENTCOMPARE_VALUE (0x56)
374 #define GPIO_01_FILTER_AMOUNT (0x58)
375 #define GPIO_01_FILTER_COUNT (0x5A)
376 #define GPIO_01_EVENT_COUNT (0x5C)
377 #define GPIO_01_EVENTCOMPARE_VALUE (0x5E)
378 #define GPIO_02_FILTER_AMOUNT (0x60)
379 #define GPIO_02_FILTER_COUNT (0x62)
380 #define GPIO_02_EVENT_COUNT (0x64)
381 #define GPIO_02_EVENTCOMPARE_VALUE (0x66)
382 #define GPIO_03_FILTER_AMOUNT (0x68)
383 #define GPIO_03_FILTER_COUNT (0x6A)
384 #define GPIO_03_EVENT_COUNT (0x6C)
385 #define GPIO_03_EVENTCOMPARE_VALUE (0x6E)
386 #define GPIO_04_FILTER_AMOUNT (0x70)
387 #define GPIO_04_FILTER_COUNT (0x72)
388 #define GPIO_04_EVENT_COUNT (0x74)
389 #define GPIO_04_EVENTCOMPARE_VALUE (0x76)
390 #define GPIO_05_FILTER_AMOUNT (0x78)
391 #define GPIO_05_FILTER_COUNT (0x7A)
392 #define GPIO_05_EVENT_COUNT (0x7C)
393 #define GPIO_05_EVENTCOMPARE_VALUE (0x7E)
394 #define GPIO_06_FILTER_AMOUNT (0x0D0)
395 #define GPIO_06_FILTER_COUNT (0x0D2)
396 #define GPIO_06_EVENT_COUNT (0x0D4)
397 #define GPIO_06_EVENTCOMPARE_VALUE (0x0D6)
398 #define GPIO_07_FILTER_AMOUNT (0x0D8)
399 #define GPIO_07_FILTER_COUNT (0x0DA)
400 #define GPIO_07_EVENT_COUNT (0x0DC)
401 #define GPIO_07_EVENTCOMPARE_VALUE (0x0DE)
403 /* R/W GPIO Interrupt &PME Mapper Registers*/
404 #define GPIO_MAPPER_X (0x0E0)
405 #define GPIO_MAPPER_Y (0x0E4)
406 #define GPIO_MAPPER_Z (0x0E8)
407 #define GPIO_MAPPER_W (0x0EC)
408 #define GPIO_FE_SELECT_0 (0x0F0)
409 #define GPIO_FE_SELECT_1 (0x0F1)
410 #define GPIO_FE_SELECT_2 (0x0F2)
411 #define GPIO_FE_SELECT_3 (0x0F3)
412 #define GPIO_FE_SELECT_4 (0x0F4)
413 #define GPIO_FE_SELECT_5 (0x0F5)
414 #define GPIO_FE_SELECT_6 (0x0F6)
415 #define GPIO_FE_SELECT_7 (0x0F7)
417 /* Event Counter Decrement Registers*/
418 #define GPIOL_IN_EVENT_DECREMENT (0x0F8)
419 #define GPIOH_IN_EVENT_DECREMENT (0x0FC)
422 #define PM_SSD (0x00)
423 #define PM_SCXA (0x04)
424 #define PM_SCYA (0x08)
425 #define PM_SODA (0x0C)
426 #define PM_SCLK (0x10)
427 #define PM_SED (0x14)
428 #define PM_SCXD (0x18)
429 #define PM_SCYD (0x1C)
430 #define PM_SIDD (0x20)
431 #define PM_WKD (0x30)
432 #define PM_WKXD (0x34)
434 #define PM_WKXA (0x3C)
435 #define PM_FSD (0x40)
436 #define PM_TSD (0x44)
437 #define PM_PSD (0x48)
438 #define PM_NWKD (0x4C)
439 #define PM_AWKD (0x50)
440 #define PM_SSC (0x54)
443 /* FLASH device macros */
444 #define FLASH_TYPE_NONE 0 /* No flash device installed */
445 #define FLASH_TYPE_NAND 1 /* NAND device */
446 #define FLASH_TYPE_NOR 2 /* NOR device */
448 #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
449 #define FLASH_IF_IO 2 /* I/O interface for Flash device */
451 /* Flash Memory Mask values */
452 #define FLASH_MEM_DEFAULT 0x00000000
453 #define FLASH_MEM_4K 0xFFFFF000
454 #define FLASH_MEM_8K 0xFFFFE000
455 #define FLASH_MEM_16K 0xFFFFC000
456 #define FLASH_MEM_128K 0xFFFE0000
457 #define FLASH_MEM_512K 0xFFFC0000
458 #define FLASH_MEM_4M 0xFFC00000
459 #define FLASH_MEM_8M 0xFF800000
460 #define FLASH_MEM_16M 0xFF000000
462 /* Flash IO Mask values */
463 #define FLASH_IO_DEFAULT 0x00000000
464 #define FLASH_IO_16B 0x0000FFF0
465 #define FLASH_IO_32B 0x0000FFE0
466 #define FLASH_IO_64B 0x0000FFC0
467 #define FLASH_IO_128B 0x0000FF80
468 #define FLASH_IO_256B 0x0000FF00
471 #endif /* _CS5536_H */