2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Nils Jacobs
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 /* SouthBridge Equates */
26 #define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
27 #define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
28 #define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
29 #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
31 #define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
32 #define SMBUS_IO_BASE 0x6000
33 #define GPIO_IO_BASE 0x6100
34 #define MFGPT_IO_BASE 0x6200
35 #define ACPI_IO_BASE 0x9C00
36 #define PMS_IO_BASE 0x9D00
38 /* Cs5536 as follows. */
42 /* port2 - USB Controller #2 */
43 /* port3 - ATA-5 Controller */
46 /* port6 - USB Controller #1 */
49 #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
50 #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
51 #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
52 #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
53 #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
54 #define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
55 #define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
56 #define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
59 #define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
62 #define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
63 #define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
66 #define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
67 #define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
70 #define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
71 #define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
72 #define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
73 #define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
76 #define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
77 #define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
80 #define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
81 #define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
82 #define GLPCI_CRTL_PPIDE_SET (1 << 17)
85 #define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
88 #define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
89 #define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
90 #define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
91 #define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
92 #define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
93 #define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
94 #define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
95 #define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
96 #define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
97 #define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
98 #define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
99 #define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
100 #define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
103 #define GPIOL_2_SET (1 << 2)
105 /* GPIO LOW Bank Bit Registers */
106 #define GPIOL_INPUT_ENABLE (0x20)
107 #define GPIOL_IN_AUX1_SELECT (0x34)
109 /* FLASH device macros */
110 #define FLASH_TYPE_NONE 0 /* No flash device installed */
111 #define FLASH_TYPE_NAND 1 /* NAND device */
113 #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
115 /* Flash Memory Mask values */
116 #define FLASH_MEM_4K 0xFFFFF000
118 #if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
119 #if defined(__PRE_RAM__)
120 void cs5535_disable_internal_uart(void);
122 void chipsetinit(void);
126 #endif /* _CS5535_H */