2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <southbridge/amd/cimx_wrapper/sb800/smbus.h>
23 static inline void smbus_delay(void)
25 outb(inb(0x80), 0x80);
28 static int smbus_wait_until_ready(u32 smbus_io_base)
32 loops = SMBUS_TIMEOUT;
35 val = inb(smbus_io_base + SMBHSTSTAT);
37 if (val == 0) { /* ready now */
40 outb(val, smbus_io_base + SMBHSTSTAT);
43 return -2; /* time out */
46 static int smbus_wait_until_done(u32 smbus_io_base)
50 loops = SMBUS_TIMEOUT;
54 val = inb(smbus_io_base + SMBHSTSTAT);
55 val &= 0x1f; /* mask off reserved bits */
57 return -5; /* error */
60 outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
65 return -3; /* timeout */
68 int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
72 if (smbus_wait_until_ready(smbus_io_base) < 0) {
73 return -2; /* not ready */
76 /* set the device I'm talking too */
77 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
79 byte = inb(smbus_io_base + SMBHSTCTRL);
80 byte &= 0xe3; /* Clear [4:2] */
81 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
82 outb(byte, smbus_io_base + SMBHSTCTRL);
84 /* poll for transaction completion */
85 if (smbus_wait_until_done(smbus_io_base) < 0) {
86 return -3; /* timeout or error */
89 /* read results of transaction */
90 byte = inb(smbus_io_base + SMBHSTCMD);
95 int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
99 if (smbus_wait_until_ready(smbus_io_base) < 0) {
100 return -2; /* not ready */
103 /* set the command... */
104 outb(val, smbus_io_base + SMBHSTCMD);
106 /* set the device I'm talking too */
107 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
109 byte = inb(smbus_io_base + SMBHSTCTRL);
110 byte &= 0xe3; /* Clear [4:2] */
111 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
112 outb(byte, smbus_io_base + SMBHSTCTRL);
114 /* poll for transaction completion */
115 if (smbus_wait_until_done(smbus_io_base) < 0) {
116 return -3; /* timeout or error */
122 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
126 if (smbus_wait_until_ready(smbus_io_base) < 0) {
127 return -2; /* not ready */
130 /* set the command/address... */
131 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
133 /* set the device I'm talking too */
134 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
136 byte = inb(smbus_io_base + SMBHSTCTRL);
137 byte &= 0xe3; /* Clear [4:2] */
138 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
139 outb(byte, smbus_io_base + SMBHSTCTRL);
141 /* poll for transaction completion */
142 if (smbus_wait_until_done(smbus_io_base) < 0) {
143 return -3; /* timeout or error */
146 /* read results of transaction */
147 byte = inb(smbus_io_base + SMBHSTDAT0);
152 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
156 if (smbus_wait_until_ready(smbus_io_base) < 0) {
157 return -2; /* not ready */
160 /* set the command/address... */
161 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
163 /* set the device I'm talking too */
164 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
167 outb(val, smbus_io_base + SMBHSTDAT0);
169 byte = inb(smbus_io_base + SMBHSTCTRL);
170 byte &= 0xe3; /* Clear [4:2] */
171 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
172 outb(byte, smbus_io_base + SMBHSTCTRL);
174 /* poll for transaction completion */
175 if (smbus_wait_until_done(smbus_io_base) < 0) {
176 return -3; /* timeout or error */
182 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
186 outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
189 * For certain revisions of the chip, the ABCFG registers,
190 * with an address of 0x100NN (where 'N' is any hexadecimal
191 * number), require an extra programming step.*/
197 /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
198 outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
203 void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
207 outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
210 * For certain revisions of the chip, the ABCFG registers,
211 * with an address of 0x100NN (where 'N' is any hexadecimal
212 * number), require an extra programming step.*/
218 //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
219 outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
224 /* space = 0: AX_INDXC, AX_DATAC
225 * space = 1: AX_INDXP, AX_DATAP
227 void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
231 /* read axindc to tmp */
232 outl(space << 29 | space << 3 | 0x30, AB_INDX);
233 outl(axindc, AB_DATA);
235 outl(space << 29 | space << 3 | 0x34, AB_INDX);
243 outl(space << 29 | space << 3 | 0x30, AB_INDX);
244 outl(axindc, AB_DATA);
246 outl(space << 29 | space << 3 | 0x34, AB_INDX);