2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include "sb800_smbus.h"
24 static inline void smbus_delay(void)
26 outb(inb(0x80), 0x80);
29 static int smbus_wait_until_ready(u32 smbus_io_base)
33 loops = SMBUS_TIMEOUT;
36 val = inb(smbus_io_base + SMBHSTSTAT);
38 if (val == 0) { /* ready now */
41 outb(val, smbus_io_base + SMBHSTSTAT);
44 return -2; /* time out */
47 static int smbus_wait_until_done(u32 smbus_io_base)
51 loops = SMBUS_TIMEOUT;
55 val = inb(smbus_io_base + SMBHSTSTAT);
56 val &= 0x1f; /* mask off reserved bits */
58 return -5; /* error */
61 outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
66 return -3; /* timeout */
69 int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
73 if (smbus_wait_until_ready(smbus_io_base) < 0) {
74 return -2; /* not ready */
77 /* set the device I'm talking too */
78 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
80 byte = inb(smbus_io_base + SMBHSTCTRL);
81 byte &= 0xe3; /* Clear [4:2] */
82 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
83 outb(byte, smbus_io_base + SMBHSTCTRL);
85 /* poll for transaction completion */
86 if (smbus_wait_until_done(smbus_io_base) < 0) {
87 return -3; /* timeout or error */
90 /* read results of transaction */
91 byte = inb(smbus_io_base + SMBHSTCMD);
96 int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
100 if (smbus_wait_until_ready(smbus_io_base) < 0) {
101 return -2; /* not ready */
104 /* set the command... */
105 outb(val, smbus_io_base + SMBHSTCMD);
107 /* set the device I'm talking too */
108 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
110 byte = inb(smbus_io_base + SMBHSTCTRL);
111 byte &= 0xe3; /* Clear [4:2] */
112 byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
113 outb(byte, smbus_io_base + SMBHSTCTRL);
115 /* poll for transaction completion */
116 if (smbus_wait_until_done(smbus_io_base) < 0) {
117 return -3; /* timeout or error */
123 int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
127 if (smbus_wait_until_ready(smbus_io_base) < 0) {
128 return -2; /* not ready */
131 /* set the command/address... */
132 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
134 /* set the device I'm talking too */
135 outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
137 byte = inb(smbus_io_base + SMBHSTCTRL);
138 byte &= 0xe3; /* Clear [4:2] */
139 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
140 outb(byte, smbus_io_base + SMBHSTCTRL);
142 /* poll for transaction completion */
143 if (smbus_wait_until_done(smbus_io_base) < 0) {
144 return -3; /* timeout or error */
147 /* read results of transaction */
148 byte = inb(smbus_io_base + SMBHSTDAT0);
153 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
157 if (smbus_wait_until_ready(smbus_io_base) < 0) {
158 return -2; /* not ready */
161 /* set the command/address... */
162 outb(address & 0xff, smbus_io_base + SMBHSTCMD);
164 /* set the device I'm talking too */
165 outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
168 outb(val, smbus_io_base + SMBHSTDAT0);
170 byte = inb(smbus_io_base + SMBHSTCTRL);
171 byte &= 0xe3; /* Clear [4:2] */
172 byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
173 outb(byte, smbus_io_base + SMBHSTCTRL);
175 /* poll for transaction completion */
176 if (smbus_wait_until_done(smbus_io_base) < 0) {
177 return -3; /* timeout or error */
183 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
187 outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
190 * For certain revisions of the chip, the ABCFG registers,
191 * with an address of 0x100NN (where 'N' is any hexadecimal
192 * number), require an extra programming step.*/
198 /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
199 outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
204 void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
208 outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
211 * For certain revisions of the chip, the ABCFG registers,
212 * with an address of 0x100NN (where 'N' is any hexadecimal
213 * number), require an extra programming step.*/
219 //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
220 outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
225 /* space = 0: AX_INDXC, AX_DATAC
226 * space = 1: AX_INDXP, AX_DATAP
228 void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
232 /* read axindc to tmp */
233 outl(space << 29 | space << 3 | 0x30, AB_INDX);
234 outl(axindc, AB_DATA);
236 outl(space << 29 | space << 3 | 0x34, AB_INDX);
244 outl(space << 29 | space << 3 | 0x30, AB_INDX);
245 outl(axindc, AB_DATA);
247 outl(space << 29 | space << 3 | 0x34, AB_INDX);