src/southbridge/amd/cimx_wrapper/sb800/sb800_late.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <device/device.h>      /* device_t */
  22 #include <device/pci.h>         /* device_operations */
  23 #include <device/pci_ids.h>
  24 #include <device/smbus.h>       /* smbus_bus_operations */
  25 #include <console/console.h>    /* printk */
  26 #include "sb800_lpc.h"          /* lpc_read_resources */
  27 #include "SBPLATFORM.h"         /* Platfrom Specific Definitions */
  28 #include "sb800_cfg.h"          /* sb800 Cimx configuration */
  29 #include "chip.h"               /* struct southbridge_amd_cimx_wrapper_sb800_config */
  30
  31
  32 /*implement in mainboard.c*/
  33 //void set_pcie_assert(void);
  34 //void set_pcie_deassert(void);
  35 void set_pcie_reset(void);
  36 void set_pcie_dereset(void);
  37
  38
  39 #ifndef _RAMSTAGE_
  40 #define _RAMSTAGE_
  41 #endif
  42 static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
  43 static AMDSBCFG *sb_config = &sb_late_cfg;
  44
  45
  46 /**
  47  * @brief Entry point of Southbridge CIMx callout
  48  *
  49  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
  50  *
  51  * @param[in] func      Southbridge CIMx Function ID.
  52  * @param[in] data      Southbridge Input Data.
  53  * @param[in] sb_config Southbridge configuration structure pointer.
  54  *
  55  */
  56 u32 sb800_callout_entry(u32 func, u32 data, void* config)
  57 {
  58         u32 ret = 0;
  59
  60         switch (func) {
  61         case CB_SBGPP_RESET_ASSERT:
  62                 //set_pcie_assert();
  63                 set_pcie_reset();
  64                 break;
  65
  66         case CB_SBGPP_RESET_DEASSERT:
  67                 //set_pcie_deassert();
  68                 set_pcie_dereset();
  69                 break;
  70
  71         case IMC_FIRMWARE_FAIL:
  72                 break;
  73
  74         default:
  75                 break;
  76         }
  77
  78         return ret;
  79 }
  80
  81
  82 static struct pci_operations lops_pci = {
  83         .set_subsystem = 0,
  84 };
  85
  86 static void lpc_enable_resources(device_t dev)
  87 {
  88
  89         pci_dev_enable_resources(dev);
  90         //lpc_enable_childrens_resources(dev);
  91 }
  92
  93 static void lpc_init(device_t dev)
  94 {
  95         /* SB Configure HPET base and enable bit */
  96         hpetInit(sb_config, &(sb_config->BuildParameters));
  97 }
  98
  99 static struct device_operations lpc_ops = {
 100         .read_resources = lpc_read_resources,
 101         .set_resources = lpc_set_resources,
 102         .enable_resources = lpc_enable_resources,
 103         .init = lpc_init,
 104         .scan_bus = scan_static_bus,
 105         .ops_pci = &lops_pci,
 106 };
 107
 108 static const struct pci_driver lpc_driver __pci_driver = {
 109         .ops = &lpc_ops,
 110         .vendor = PCI_VENDOR_ID_ATI,
 111         .device = PCI_DEVICE_ID_ATI_SB800_LPC,
 112 };
 113
 114
 115 static void sata_enable_resources(struct device *dev)
 116 {
 117         sataInitAfterPciEnum(sb_config);
 118         pci_dev_enable_resources(dev);
 119 }
 120
 121 static void sata_init(struct device *dev)
 122 {
 123         sb_config->StdHeader.Func = SB_MID_POST_INIT;
 124         AmdSbDispatcher(sb_config); //sataInitMidPost only
 125         commonInitLateBoot(sb_config);
 126         sataInitLatePost(sb_config);
 127 }
 128
 129 static struct device_operations sata_ops = {
 130         .read_resources = pci_dev_read_resources,
 131         .set_resources = pci_dev_set_resources,
 132         .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
 133         .init = sata_init,
 134         .scan_bus = 0,
 135         .ops_pci = &lops_pci,
 136 };
 137
 138 static const struct pci_driver sata_driver __pci_driver = {
 139         .ops = &sata_ops,
 140         .vendor = PCI_VENDOR_ID_ATI,
 141         .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
 142 };
 143
 144
 145 #if CONFIG_USBDEBUG
 146 static void usb_set_resources(struct device *dev)
 147 {
 148         struct resource *res;
 149         u32 base;
 150         u32 old_debug;
 151
 152         old_debug = get_ehci_debug();
 153         set_ehci_debug(0);
 154
 155         pci_dev_set_resources(dev);
 156
 157         res = find_resource(dev, 0x10);
 158         set_ehci_debug(old_debug);
 159         if (!res)
 160                 return;
 161         base = res->base;
 162         set_ehci_base(base);
 163         report_resource_stored(dev, res, "");
 164 }
 165 #endif
 166
 167 static void usb_init(struct device *dev)
 168 {
 169         usbInitAfterPciInit(sb_config);
 170         commonInitLateBoot(sb_config);
 171 }
 172
 173 static struct device_operations usb_ops = {
 174         .read_resources = pci_dev_read_resources,
 175 #if CONFIG_USBDEBUG
 176         .set_resources = usb_set_resources,
 177 #else
 178         .set_resources = pci_dev_set_resources,
 179 #endif
 180         .enable_resources = pci_dev_enable_resources,
 181         .init = usb_init,
 182         .scan_bus = 0,
 183         .ops_pci = &lops_pci,
 184 };
 185
 186 /*
 187  * The pci id of usb ctrl 0 and 1 are the same.
 188  */
 189 static const struct pci_driver usb_ohci123_driver __pci_driver = {
 190         .ops = &usb_ops,
 191         .vendor = PCI_VENDOR_ID_ATI,
 192         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
 193 };
 194
 195 static const struct pci_driver usb_ehci123_driver __pci_driver = {
 196         .ops = &usb_ops,
 197         .vendor = PCI_VENDOR_ID_ATI,
 198         .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
 199 };
 200
 201 static const struct pci_driver usb_ohci4_driver __pci_driver = {
 202         .ops = &usb_ops,
 203         .vendor = PCI_VENDOR_ID_ATI,
 204         .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
 205 };
 206
 207
 208 static void azalia_init(struct device *dev)
 209 {
 210         azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
 211 }
 212
 213 static struct device_operations azalia_ops = {
 214         .read_resources = pci_dev_read_resources,
 215         .set_resources = pci_dev_set_resources,
 216         .enable_resources = pci_dev_enable_resources,
 217         .init = azalia_init,
 218         .scan_bus = 0,
 219         .ops_pci = &lops_pci,
 220 };
 221
 222 static const struct pci_driver azalia_driver __pci_driver = {
 223         .ops = &azalia_ops,
 224         .vendor = PCI_VENDOR_ID_ATI,
 225         .device = PCI_DEVICE_ID_ATI_SB800_HDA,
 226 };
 227
 228
 229 static void gec_init(struct device *dev)
 230 {
 231         gecInitAfterPciEnum(sb_config);
 232         gecInitLatePost(sb_config);
 233         printk(BIOS_DEBUG, "gec hda enabled\n");
 234 }
 235
 236 static struct device_operations gec_ops = {
 237         .read_resources = pci_dev_read_resources,
 238         .set_resources = pci_dev_set_resources,
 239         .enable_resources = pci_dev_enable_resources,
 240         .init = gec_init,
 241         .scan_bus = 0,
 242         .ops_pci = &lops_pci,
 243 };
 244
 245 static const struct pci_driver gec_driver __pci_driver = {
 246         .ops = &gec_ops,
 247         .vendor = PCI_VENDOR_ID_ATI,
 248         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 249 };
 250
 251
 252 static void pcie_init(device_t dev)
 253 {
 254         sbPcieGppLateInit(sb_config);
 255 }
 256
 257 static struct device_operations pci_ops = {
 258         .read_resources = pci_bus_read_resources,
 259         .set_resources = pci_dev_set_resources,
 260         .enable_resources = pci_bus_enable_resources,
 261         .init = pcie_init,
 262         .scan_bus = pci_scan_bridge,
 263         .reset_bus = pci_bus_reset,
 264         .ops_pci = &lops_pci,
 265 };
 266
 267 static const struct pci_driver pci_driver __pci_driver = {
 268         .ops = &pci_ops,
 269         .vendor = PCI_VENDOR_ID_ATI,
 270         .device = PCI_DEVICE_ID_ATI_SB800_PCI,
 271 };
 272
 273
 274 struct device_operations bridge_ops = {
 275         .read_resources   = pci_bus_read_resources,
 276         .set_resources    = pci_dev_set_resources,
 277         .enable_resources = pci_bus_enable_resources,
 278         .init             = pcie_init,
 279         .scan_bus         = pci_scan_bridge,
 280         .enable           = 0,
 281         .reset_bus        = pci_bus_reset,
 282         .ops_pci          = &lops_pci,
 283 };
 284
 285 /* 0:15:0 PCIe PortA */
 286 static const struct pci_driver PORTA_driver __pci_driver = {
 287         .ops = &bridge_ops,
 288         .vendor = PCI_VENDOR_ID_ATI,
 289         .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
 290 };
 291
 292 /* 0:15:1 PCIe PortB */
 293 static const struct pci_driver PORTB_driver __pci_driver = {
 294         .ops = &bridge_ops,
 295         .vendor = PCI_VENDOR_ID_ATI,
 296         .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
 297 };
 298
 299 /* 0:15:2 PCIe PortC */
 300 static const struct pci_driver PORTC_driver __pci_driver = {
 301         .ops = &bridge_ops,
 302         .vendor = PCI_VENDOR_ID_ATI,
 303         .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
 304 };
 305
 306 /* 0:15:3 PCIe PortD */
 307 static const struct pci_driver PORTD_driver __pci_driver = {
 308         .ops = &bridge_ops,
 309         .vendor = PCI_VENDOR_ID_ATI,
 310         .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
 311 };
 312
 313
 314 /**
 315  * @brief SB Cimx entry point sbBeforePciInit wrapper
 316  */
 317 static void sb800_enable(device_t dev)
 318 {
 319         u8 gpp_port = 0;
 320         struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
 321                 (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
 322
 323         sb800_cimx_config(sb_config);
 324         printk(BIOS_DEBUG, "sb800_enable() ");
 325
 326         /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
 327         commonInitEarlyBoot(sb_config);
 328         commonInitEarlyPost(sb_config);
 329
 330         switch (dev->path.pci.devfn) {
 331         case (0x11 << 3) | 0: /* 0:11.0  SATA */
 332                 if (dev->enabled) {
 333                         sb_config->SATAMODE.SataMode.SataController = ENABLED;
 334                         if (1 == sb_chip->boot_switch_sata_ide)
 335                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
 336                         else if (0 == sb_chip->boot_switch_sata_ide)
 337                                 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
 338                 } else {
 339                         sb_config->SATAMODE.SataMode.SataController = DISABLED;
 340                 }
 341
 342                 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 343                 break;
 344
 345         case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 346         case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
 347         case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
 348         case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
 349         case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
 350         case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
 351         case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 352                 usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
 353                 break;
 354
 355         case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
 356                 break;
 357
 358         case (0x14 << 3) | 1: /* 0:14:1 IDE */
 359                 if (dev->enabled) {
 360                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
 361                 } else {
 362                         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
 363                 }
 364                 sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
 365                 break;
 366
 367         case (0x14 << 3) | 2: /* 0:14:2 HDA */
 368                 if (dev->enabled) {
 369                         if (AZALIA_DISABLE == sb_config->AzaliaController) {
 370                                 sb_config->AzaliaController = AZALIA_AUTO;
 371                         }
 372                         printk(BIOS_DEBUG, "hda enabled\n");
 373                 } else {
 374                         sb_config->AzaliaController = AZALIA_DISABLE;
 375                         printk(BIOS_DEBUG, "hda disabled\n");
 376                 }
 377                 azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
 378                 break;
 379
 380
 381         case (0x14 << 3) | 3: /* 0:14:3 LPC */
 382                 break;
 383
 384         case (0x14 << 3) | 4: /* 0:14:4 PCI */
 385                 break;
 386
 387         case (0x14 << 3) | 6: /* 0:14:6 GEC */
 388                 if (dev->enabled) {
 389                         sb_config->GecConfig = 0;
 390                         printk(BIOS_DEBUG, "gec enabled\n");
 391                 } else {
 392                         sb_config->GecConfig = 1;
 393                         printk(BIOS_DEBUG, "gec disabled\n");
 394                 }
 395                 gecInitBeforePciEnum(sb_config); // Init GEC
 396                 break;
 397
 398         case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
 399         case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
 400         case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
 401         case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
 402                 gpp_port = (dev->path.pci.devfn) & 0x03;
 403                 if (dev->enabled) {
 404                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
 405                 } else {
 406                         sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
 407                 }
 408
 409                 /*
 410                  * GPP_CFGMODE_X4000: PortA Lanes[3:0]
 411                  * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
 412                  * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 413                  * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 414                  */
 415                 if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
 416                         sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 417                 }
 418
 419                 sbPcieGppEarlyInit(sb_config);
 420                 break;
 421
 422         default:
 423                 break;
 424         }
 425
 426         /* Special setting ABCFG registers before PCI emulation. */
 427         abSpecialSetBeforePciEnum(sb_config);
 428         usbDesertPll(sb_config);
 429         //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
 430         //AmdSbDispatcher(sb_config);
 431 }
 432
 433 struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
 434         CHIP_NAME("ATI SB800")
 435         .enable_dev = sb800_enable,
 436 };