src/southbridge/amd/cimx_wrapper/sb800/lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <device/pci.h>
  21 #include <southbridge/amd/cimx_wrapper/sb800/lpc.h>
  22
  23 void lpc_read_resources(device_t dev)
  24 {
  25         struct resource *res;
  26
  27         /* Get the normal pci resources of this device */
  28         pci_dev_read_resources(dev);    /* We got one for APIC, or one more for TRAP */
  29
  30         pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
  31
  32         /* Add an extra subtractive resource for both memory and I/O. */
  33         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  34         res->base = 0;
  35         res->size = 0x1000;
  36         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
  37                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  38
  39         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  40         res->base = 0xff800000;
  41         res->size = 0x00800000; /* 8 MB for flash */
  42         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
  43                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  44
  45         res = new_resource(dev, 3); /* IOAPIC */
  46         res->base = 0xfec00000;
  47         res->size = 0x00001000;
  48         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  49
  50         compact_resources(dev);
  51 }
  52
  53 void lpc_set_resources(struct device *dev)
  54 {
  55         struct resource *res;
  56
  57         pci_dev_set_resources(dev);
  58
  59         /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
  60         res = find_resource(dev, SPIROM_BASE_ADDRESS);
  61         pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
  62 }
  63
  64 /**
  65  * @brief Enable resources for children devices
  66  *
  67  * @param dev the device whos children's resources are to be enabled
  68  *
  69  */
  70 void lpc_enable_childrens_resources(device_t dev)
  71 {
  72         struct bus *link;
  73         u32 reg, reg_x;
  74         int var_num = 0;
  75         u16 reg_var[3];
  76
  77         reg = pci_read_config32(dev, 0x44);
  78         reg_x = pci_read_config32(dev, 0x48);
  79
  80         for (link = dev->link_list; link; link = link->next) {
  81                 device_t child;
  82                 for (child = link->children; child;
  83                      child = child->sibling) {
  84                         if (child->enabled
  85                             && (child->path.type == DEVICE_PATH_PNP)) {
  86                                 struct resource *res;
  87                                 for (res = child->resource_list; res; res = res->next) {
  88                                         u32 base, end;  /*  don't need long long */
  89                                         if (!(res->flags & IORESOURCE_IO))
  90                                                 continue;
  91                                         base = res->base;
  92                                         end = resource_end(res);
  93 /*
  94                                         printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
  95                                              dev_path(child), base, end);
  96 */
  97                                         switch (base) {
  98                                         case 0x60:      /*  KB */
  99                                         case 0x64:      /*  MS */
 100                                                 reg |= (1 << 29);
 101                                                 break;
 102                                         case 0x3f8:     /*  COM1 */
 103                                                 reg |= (1 << 6);
 104                                                 break;
 105                                         case 0x2f8:     /*  COM2 */
 106                                                 reg |= (1 << 7);
 107                                                 break;
 108                                         case 0x378:     /*  Parallal 1 */
 109                                                 reg |= (1 << 0);
 110                                                 break;
 111                                         case 0x3f0:     /*  FD0 */
 112                                                 reg |= (1 << 26);
 113                                                 break;
 114                                         case 0x220:     /*  Aduio 0 */
 115                                                 reg |= (1 << 8);
 116                                                 break;
 117                                         case 0x300:     /*  Midi 0 */
 118                                                 reg |= (1 << 18);
 119                                                 break;
 120                                         case 0x400:
 121                                                 reg_x |= (1 << 16);
 122                                                 break;
 123                                         case 0x480:
 124                                                 reg_x |= (1 << 17);
 125                                                 break;
 126                                         case 0x500:
 127                                                 reg_x |= (1 << 18);
 128                                                 break;
 129                                         case 0x580:
 130                                                 reg_x |= (1 << 19);
 131                                                 break;
 132                                         case 0x4700:
 133                                                 reg_x |= (1 << 22);
 134                                                 break;
 135                                         case 0xfd60:
 136                                                 reg_x |= (1 << 23);
 137                                                 break;
 138                                         default:
 139                                                 if (var_num >= 3)
 140                                                         continue;       /* only 3 var ; compact them ? */
 141                                                 switch (var_num) {
 142                                                 case 0:
 143                                                         reg_x |= (1 << 2);
 144                                                         break;
 145                                                 case 1:
 146                                                         reg_x |= (1 << 24);
 147                                                         break;
 148                                                 case 2:
 149                                                         reg_x |= (1 << 25);
 150                                                         break;
 151                                                 }
 152                                                 reg_var[var_num++] =
 153                                                     base & 0xffff;
 154                                         }
 155                                 }
 156                         }
 157                 }
 158         }
 159         pci_write_config32(dev, 0x44, reg);
 160         pci_write_config32(dev, 0x48, reg_x);
 161         /* Set WideIO for as many IOs found (fall through is on purpose) */
 162         switch (var_num) {
 163         case 2:
 164                 pci_write_config16(dev, 0x90, reg_var[2]);
 165         case 1:
 166                 pci_write_config16(dev, 0x66, reg_var[1]);
 167         case 0:
 168                 //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
 169                 break;
 170         }
 171 }