src/southbridge/amd/cimx_wrapper/sb800/cfg.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h>
  21 #include <southbridge/amd/cimx_wrapper/sb800/cfg.h>
  22
  23 /**
  24  * @brief South Bridge CIMx configuration
  25  *
  26  * should be called before exeucte CIMx function.
  27  * this function will be called in romstage and ramstage.
  28  */
  29 void sb800_cimx_config(AMDSBCFG *sb_config)
  30 {
  31         if (!sb_config) {
  32                 return;
  33         }
  34         //memset(sb_config, 0, sizeof(AMDSBCFG));
  35
  36         /* header */
  37         sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
  38
  39         /* static Build Parameters */
  40         sb_config->BuildParameters.BiosSize = BIOS_SIZE;
  41         sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
  42         sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
  43         sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
  44         sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
  45         sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
  46         sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
  47         sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
  48         sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
  49         sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
  50         sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
  51         sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
  52         sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
  53         sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
  54         sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
  55         sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
  56         sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
  57         sb_config->BuildParameters.OhciSsid = OHCI_SSID;
  58         sb_config->BuildParameters.EhciSsid = EHCI_SSID;
  59         sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
  60         sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
  61         sb_config->BuildParameters.IdeSsid = IDE_SSID;
  62         sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
  63         sb_config->BuildParameters.LpcSsid = LPC_SSID;
  64         sb_config->BuildParameters.PCIBSsid = PCIB_SSID;
  65         sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type;
  66         sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
  67
  68         /* General */
  69         sb_config->SpreadSpectrum = SPREAD_SPECTRUM;
  70         sb_config->PciClks = PCI_CLOCK_CTRL;
  71         sb_config->HpetTimer = HPET_TIMER;
  72
  73         /* USB */
  74         sb_config->USBMODE.UsbModeReg = USB_CINFIG;
  75         sb_config->SbUsbPll = 0;
  76
  77         /* SATA */
  78         sb_config->SataClass = SATA_MODE;
  79         sb_config->SataIdeMode = SATA_IDE_MODE;
  80         sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
  81         sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
  82         sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
  83                                                                 //TODO: set to secondary not take effect.
  84         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
  85         sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
  86
  87         /* Azalia HDA */
  88         sb_config->AzaliaController = AZALIA_CONTROLLER;
  89         sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
  90         sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
  91         sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
  92
  93         /*
  94          * GPP. default configure only enable port0 with 4 lanes,
  95          * configure in devicetree.cb would overwrite the default configuration
  96          */
  97         sb_config->GppFunctionEnable = GPP_CONTROLLER;
  98         sb_config->GppLinkConfig = GPP_CFGMODE;
  99         //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
 100         sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
 101         sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
 102         sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
 103         sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
 104         sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
 105         //sb_config->NbSbGen2 = TRUE;
 106         //sb_config->GppGen2 = TRUE;
 107
 108         //cimx BTS fix
 109         sb_config->GppMemWrImprove = TRUE;
 110         sb_config->SbPcieOrderRule = TRUE;
 111         sb_config->AlinkPhyPllPowerDown = TRUE;
 112         sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
 113         sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong
 114         sb_config->GecConfig = 0; //ENABLE GEC controller
 115
 116 #ifndef __PRE_RAM__
 117         /* ramstage cimx config here */
 118         if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
 119                 sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
 120         }
 121
 122         //sb_config->
 123 #endif //!__PRE_RAM__
 124 }