2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_ids.h>
24 #include <arch/io.h> /* inl, outl */
25 #include <arch/romcc_io.h> /* device_t */
26 #include "SBPLATFORM.h"
28 #include "cfg.h" /*sb800_cimx_config*/
31 #if CONFIG_RAMINIT_SYSINFO == 1
33 * @brief Get SouthBridge device number
34 * @param[in] bus target bus number
35 * @return southbridge device number
41 printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
42 //dev = PCI_DEV(bus, 0x14, 0);
43 dev = pci_locate_device_on_bus(
44 PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
47 printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__);
48 return (dev >> 15) & 0x1f;
54 * @brief South Bridge CIMx romstage entry,
55 * wrapper of sbPowerOnInit entry point.
57 void sb_Poweron_Init(void)
59 AMDSBCFG sb_early_cfg;
61 sb800_cimx_config(&sb_early_cfg);
62 //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
63 //AmdSbDispatcher(&sb_early_cfg);
65 //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
66 // VerifyImage() will fail, LocateImage() take minitues to find the image.
67 sbPowerOnInit(&sb_early_cfg);
71 * CIMX not set the clock to 48Mhz until sbBeforePciInit,
72 * coreboot may need to set this even more earlier
74 void sb800_clk_output_48Mhz(void)
76 /* AcpiMMioDecodeEn */
77 RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
79 *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
80 *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */