src/southbridge/amd/cimx/sb800/cfg.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include "SBPLATFORM.h"
  22 #include "cfg.h"
  23
  24
  25 /**
  26  * @brief South Bridge CIMx configuration
  27  *
  28  * should be called before exeucte CIMx function.
  29  * this function will be called in romstage and ramstage.
  30  */
  31 void sb800_cimx_config(AMDSBCFG *sb_config)
  32 {
  33         if (!sb_config) {
  34                 return;
  35         }
  36         //memset(sb_config, 0, sizeof(AMDSBCFG));
  37
  38         /* header */
  39         sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
  40
  41         /* static Build Parameters */
  42         sb_config->BuildParameters.BiosSize = BIOS_SIZE;
  43         sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
  44         sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
  45         sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
  46         sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
  47         sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
  48         sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
  49         sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
  50         sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
  51         sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS;
  52         sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
  53         sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
  54         sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
  55         sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
  56         sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
  57         sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
  58         sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
  59         sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
  60         sb_config->BuildParameters.OhciSsid = OHCI_SSID;
  61         sb_config->BuildParameters.EhciSsid = EHCI_SSID;
  62         sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
  63         sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
  64         sb_config->BuildParameters.IdeSsid = IDE_SSID;
  65         sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
  66         sb_config->BuildParameters.LpcSsid = LPC_SSID;
  67         sb_config->BuildParameters.PCIBSsid = PCIB_SSID;
  68         sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type;
  69         sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
  70
  71         /* General */
  72         sb_config->SpreadSpectrum = SPREAD_SPECTRUM;
  73         sb_config->PciClks = PCI_CLOCK_CTRL;
  74         sb_config->HpetTimer = HPET_TIMER;
  75
  76         /* USB */
  77         sb_config->USBMODE.UsbModeReg = USB_CONFIG;
  78         sb_config->SbUsbPll = 0;
  79
  80         /* SATA */
  81         sb_config->SataClass = SATA_MODE;
  82         sb_config->SataIdeMode = SATA_IDE_MODE;
  83         sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
  84         sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
  85         sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
  86                                                                 //TODO: set to secondary not take effect.
  87         sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE;
  88         sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
  89
  90         /* Azalia HDA */
  91         sb_config->AzaliaController = AZALIA_CONTROLLER;
  92         sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
  93         sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
  94         sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
  95
  96         /* LPC */
  97         /* SuperIO hardware monitor register access */
  98         sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
  99
 100         /*
 101          * GPP. default configure only enable port0 with 4 lanes,
 102          * configure in devicetree.cb would overwrite the default configuration
 103          */
 104         sb_config->GppFunctionEnable = GPP_CONTROLLER;
 105         sb_config->GppLinkConfig = GPP_CFGMODE;
 106         //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
 107         sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 108         sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 109         sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 110         sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED;
 111         sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS;
 112         sb_config->NbSbGen2 = NB_SB_GEN2;
 113         sb_config->GppGen2 = SB_GPP_GEN2;
 114
 115         //cimx BTS fix
 116         sb_config->GppMemWrImprove = TRUE;
 117         sb_config->SbPcieOrderRule = TRUE;
 118         sb_config->AlinkPhyPllPowerDown = TRUE;
 119         sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
 120         sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06
 121         sb_config->GecConfig = GEC_CONFIG;
 122
 123 #ifndef __PRE_RAM__
 124         /* ramstage cimx config here */
 125         if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
 126                 sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
 127         }
 128 #endif //!__PRE_RAM__
 129 }
 130