1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ids.h>
5 #include <device/pci_ops.h>
6 #include <device/smbus.h>
7 #include <pc80/mc146818rtc.h>
11 #include "amd8111_smbus.h"
13 #define PREVIOUS_POWER_STATE 0x43
14 #define MAINBOARD_POWER_OFF 0
15 #define MAINBOARD_POWER_ON 1
16 #define SLOW_CPU_OFF 0
17 #define SLOW_CPU__ON 1
19 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
20 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
24 static int lsmbus_recv_byte(device_t dev)
29 device = dev->path.i2c.device;
30 res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
32 return do_smbus_recv_byte(res->base, device);
35 static int lsmbus_send_byte(device_t dev, uint8_t val)
40 device = dev->path.i2c.device;
41 res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
43 return do_smbus_send_byte(res->base, device, val);
47 static int lsmbus_read_byte(device_t dev, uint8_t address)
52 device = dev->path.i2c.device;
53 res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
55 return do_smbus_read_byte(res->base, device, address);
58 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
63 device = dev->path.i2c.device;
64 res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
66 return do_smbus_write_byte(res->base, device, address, val);
69 #if CONFIG_GENERATE_ACPI_TABLES == 1
73 static void acpi_init(struct device *dev)
82 printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
83 byte = pci_read_config8(dev, 0x49);
84 pci_write_config8(dev, 0x49, byte | (1<<2));
87 byte = pci_read_config8(dev, 0x41);
88 pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
90 /* added from sourceforge */
91 byte = pci_read_config8(dev, 0x48);
92 pci_write_config8(dev, 0x48, byte | (1<<3));
94 printk(BIOS_DEBUG, "done.\n");
97 printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
98 word = pci_read_config16(dev, 0x46);
99 pci_write_config16(dev, 0x46, word | (1<<9));
100 printk(BIOS_DEBUG, "done.\n");
103 /* To enable the register 0xcf9 in the IO space
104 * bit [D5] is set in the amd8111 configuration register.
105 * The config. reg. is devBx41. Register 0xcf9 allows
106 * hard reset capability to the system. For the ACPI
107 * reset.reg values in fadt.c to work this register
110 byte = pci_read_config8(dev, 0x41);
111 pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
113 /* power on after power fail */
114 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
115 get_option(&on, "power_on_after_fail");
116 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
121 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
122 printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
124 /* switch serial irq logic from quiet mode to continuous
125 * mode for Winbond W83627HF Rev. 17
127 byte = pci_read_config8(dev, 0x4a);
128 pci_write_config8(dev, 0x4a, byte | (1<<6));
130 /* Throttle the CPU speed down for testing */
132 get_option(&on, "slow_cpu");
134 pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
135 outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
136 dword = inl(pm10_bar + 0x10);
138 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
139 (on*12)+(on>>1),(on&1)*5);
142 #if CONFIG_GENERATE_ACPI_TABLES == 1
143 pm_base = pci_read_config16(dev, 0x58) & 0xff00;
144 printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
149 static void acpi_read_resources(device_t dev)
151 struct resource *resource;
153 /* Handle the generic bars */
154 pci_dev_read_resources(dev);
156 /* Add the ACPI/SMBUS bar */
157 resource = new_resource(dev, 0x58);
159 resource->size = 256;
160 resource->align = log2(256);
161 resource->gran = log2(256);
162 resource->limit = 65536;
163 resource->flags = IORESOURCE_IO;
164 resource->index = 0x58;
167 static void acpi_enable_resources(device_t dev)
170 /* Enable the generic pci resources */
171 pci_dev_enable_resources(dev);
173 /* Enable the ACPI/SMBUS Bar */
174 byte = pci_read_config8(dev, 0x41);
176 pci_write_config8(dev, 0x41, byte);
178 /* Set the class code */
179 pci_write_config32(dev, 0x60, 0x06800000);
183 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
185 pci_write_config32(dev, 0x7c,
186 ((device & 0xffff) << 16) | (vendor & 0xffff));
189 static struct smbus_bus_operations lops_smbus_bus = {
190 .recv_byte = lsmbus_recv_byte,
191 .send_byte = lsmbus_send_byte,
192 .read_byte = lsmbus_read_byte,
193 .write_byte = lsmbus_write_byte,
196 static struct pci_operations lops_pci = {
197 .set_subsystem = lpci_set_subsystem,
200 static struct device_operations acpi_ops = {
201 .read_resources = acpi_read_resources,
202 .set_resources = pci_dev_set_resources,
203 .enable_resources = acpi_enable_resources,
205 .scan_bus = scan_static_bus,
206 /* We don't need amd8111_enable, chip ops takes care of it.
207 * It could be useful if these devices were not
208 * enabled by default.
210 // .enable = amd8111_enable,
211 .ops_pci = &lops_pci,
212 .ops_smbus_bus = &lops_smbus_bus,
215 static const struct pci_driver acpi_driver __pci_driver = {
217 .vendor = PCI_VENDOR_ID_AMD,
218 .device = PCI_DEVICE_ID_AMD_8111_ACPI,