src/southbridge/amd/amd8111/acpi.c

   1 #include <console/console.h>
   2 #include <device/device.h>
   3 #include <device/pci.h>
   4 #include <device/pci_ids.h>
   5 #include <device/pci_ops.h>
   6 #include <device/smbus.h>
   7 #include <pc80/mc146818rtc.h>
   8 #include <bitops.h>
   9 #include <arch/io.h>
  10 #include "amd8111.h"
  11 #include "amd8111_smbus.h"
  12
  13 #define PREVIOUS_POWER_STATE 0x43
  14 #define MAINBOARD_POWER_OFF 0
  15 #define MAINBOARD_POWER_ON 1
  16 #define SLOW_CPU_OFF 0
  17 #define SLOW_CPU__ON 1
  18
  19 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  20 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  21 #endif
  22
  23
  24 static int lsmbus_recv_byte(device_t dev)
  25 {
  26         unsigned device;
  27         struct resource *res;
  28
  29         device = dev->path.i2c.device;
  30         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  31
  32         return do_smbus_recv_byte(res->base, device);
  33 }
  34
  35 static int lsmbus_send_byte(device_t dev, uint8_t val)
  36 {
  37         unsigned device;
  38         struct resource *res;
  39
  40         device = dev->path.i2c.device;
  41         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  42
  43         return do_smbus_send_byte(res->base, device, val);
  44 }
  45
  46
  47 static int lsmbus_read_byte(device_t dev, uint8_t address)
  48 {
  49         unsigned device;
  50         struct resource *res;
  51
  52         device = dev->path.i2c.device;
  53         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  54
  55         return do_smbus_read_byte(res->base, device, address);
  56 }
  57
  58 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
  59 {
  60         unsigned device;
  61         struct resource *res;
  62
  63         device = dev->path.i2c.device;
  64         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  65
  66         return do_smbus_write_byte(res->base, device, address, val);
  67 }
  68
  69 static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 bytes, u8 *buffer)
  70 {
  71         unsigned device;
  72         struct resource *res;
  73
  74         device = dev->path.i2c.device;
  75         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  76
  77         return do_smbus_block_read(res->base, device, cmd, bytes, buffer);
  78 }
  79
  80 static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer)
  81 {
  82         unsigned device;
  83         struct resource *res;
  84
  85         device = dev->path.i2c.device;
  86         res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
  87
  88         return do_smbus_block_write(res->base, device, cmd, bytes, buffer);
  89 }
  90
  91
  92 #if CONFIG_GENERATE_ACPI_TABLES == 1
  93 unsigned pm_base;
  94 #endif
  95
  96 static void acpi_init(struct device *dev)
  97 {
  98         uint8_t byte;
  99         uint16_t pm10_bar;
 100         uint32_t dword;
 101         int on;
 102
 103 #if 0
 104         uint16_t word;
 105         printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
 106         byte = pci_read_config8(dev, 0x49);
 107         pci_write_config8(dev, 0x49, byte | (1<<2));
 108
 109
 110         byte = pci_read_config8(dev, 0x41);
 111         pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
 112
 113         /* added from sourceforge */
 114         byte = pci_read_config8(dev, 0x48);
 115         pci_write_config8(dev, 0x48, byte | (1<<3));
 116
 117         printk(BIOS_DEBUG, "done.\n");
 118
 119
 120         printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
 121         word = pci_read_config16(dev, 0x46);
 122         pci_write_config16(dev, 0x46, word | (1<<9));
 123         printk(BIOS_DEBUG, "done.\n");
 124 #endif
 125
 126         /* To enable the register 0xcf9 in the IO space
 127          * bit [D5] is set in the amd8111 configuration register.
 128          * The config. reg. is devBx41.  Register 0xcf9 allows
 129          * hard reset capability to the system.  For the ACPI
 130          * reset.reg values in fadt.c to work this register
 131          * must be enabled.
 132          */
 133         byte = pci_read_config8(dev, 0x41);
 134         pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
 135
 136         /* power on after power fail */
 137         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 138         get_option(&on, "power_on_after_fail");
 139         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 140         byte &= ~0x40;
 141         if (!on) {
 142                 byte |= 0x40;
 143         }
 144         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 145         printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
 146
 147         /* switch serial irq logic from quiet mode to continuous
 148          * mode for Winbond W83627HF Rev. 17
 149          */
 150         byte = pci_read_config8(dev, 0x4a);
 151         pci_write_config8(dev, 0x4a, byte | (1<<6));
 152
 153         /* Throttle the CPU speed down for testing */
 154         on = SLOW_CPU_OFF;
 155         get_option(&on, "slow_cpu");
 156         if(on) {
 157                 pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
 158                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 159                 dword = inl(pm10_bar + 0x10);
 160                 on = 8-on;
 161                 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 162                                 (on*12)+(on>>1),(on&1)*5);
 163         }
 164
 165 #if CONFIG_GENERATE_ACPI_TABLES == 1
 166         pm_base = pci_read_config16(dev, 0x58) & 0xff00;
 167         printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
 168 #endif
 169
 170 }
 171
 172 static void acpi_read_resources(device_t dev)
 173 {
 174         struct resource *resource;
 175
 176         /* Handle the generic bars */
 177         pci_dev_read_resources(dev);
 178
 179         /* Add the ACPI/SMBUS bar */
 180         resource = new_resource(dev, 0x58);
 181         resource->base  = 0;
 182         resource->size  = 256;
 183         resource->align = log2(256);
 184         resource->gran  = log2(256);
 185         resource->limit = 65536;
 186         resource->flags = IORESOURCE_IO;
 187         resource->index = 0x58;
 188 }
 189
 190 static void acpi_enable_resources(device_t dev)
 191 {
 192         uint8_t byte;
 193         /* Enable the generic pci resources */
 194         pci_dev_enable_resources(dev);
 195
 196         /* Enable the ACPI/SMBUS Bar */
 197         byte = pci_read_config8(dev, 0x41);
 198         byte |= (1 << 7);
 199         pci_write_config8(dev, 0x41, byte);
 200
 201         /* Set the class code */
 202         pci_write_config32(dev, 0x60, 0x06800000);
 203
 204 }
 205
 206 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 207 {
 208         pci_write_config32(dev, 0x7c,
 209                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 210 }
 211
 212 static struct smbus_bus_operations lops_smbus_bus = {
 213         .recv_byte  = lsmbus_recv_byte,
 214         .send_byte  = lsmbus_send_byte,
 215         .read_byte  = lsmbus_read_byte,
 216         .write_byte = lsmbus_write_byte,
 217         .block_read = lsmbus_block_read,
 218         .block_write= lsmbus_block_write,
 219 };
 220
 221 static struct pci_operations lops_pci = {
 222         .set_subsystem = lpci_set_subsystem,
 223 };
 224
 225 static struct device_operations acpi_ops  = {
 226         .read_resources   = acpi_read_resources,
 227         .set_resources    = pci_dev_set_resources,
 228         .enable_resources = acpi_enable_resources,
 229         .init             = acpi_init,
 230         .scan_bus         = scan_static_bus,
 231         /*  We don't need amd8111_enable, chip ops takes care of it.
 232          *  It could be useful if these devices were not
 233          *  enabled by default.
 234          */
 235 //      .enable           = amd8111_enable,
 236         .ops_pci          = &lops_pci,
 237         .ops_smbus_bus    = &lops_smbus_bus,
 238 };
 239
 240 static const struct pci_driver acpi_driver __pci_driver = {
 241         .ops    = &acpi_ops,
 242         .vendor = PCI_VENDOR_ID_AMD,
 243         .device = PCI_DEVICE_ID_AMD_8111_ACPI,
 244 };
 245