src/northbridge/via/vx800/vga.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* Note: Some of the VGA control registers are located on the memory controller.
  21    Registers are set both in raminit.c and northbridge.c */
  22
  23 #include <console/console.h>
  24 #include <arch/io.h>
  25 #include <stdint.h>
  26 #include <device/device.h>
  27 #include <device/pci.h>
  28 #include <device/pci_ids.h>
  29 #include <stdlib.h>
  30 #include <string.h>
  31 #include <bitops.h>
  32 #include <cpu/cpu.h>
  33 #include <cpu/x86/mtrr.h>
  34 #include <cpu/x86/msr.h>
  35 #include <arch/interrupt.h>
  36 #include "chip.h"
  37 #include "northbridge.h"
  38
  39 /* PCI Domain 1 Device 0 Function 0 */
  40
  41 #define SR_INDEX        0x3c4
  42 #define SR_DATA         0x3c5
  43 #define CRTM_INDEX      0x3b4
  44 #define CRTM_DATA       0x3b5
  45 #define CRTC_INDEX      0x3d4
  46 #define CRTC_DATA       0x3d5
  47
  48 /* !!FIXME!! These were CONFIG_ options.  Fix it in uma_ram_setting.c too. */
  49 #define VIACONFIG_VGA_PCI_10 0xf8000008
  50 #define VIACONFIG_VGA_PCI_14 0xfc000000
  51
  52 static int via_vx800_int15_handler(struct eregs *regs)
  53 {
  54         int res=-1;
  55         printk(BIOS_DEBUG, "via_vx800_int15_handler\n");
  56         switch(regs->eax & 0xffff) {
  57         case 0x5f19:
  58                 regs->eax=0x5f;
  59                 regs->ecx=0x03;
  60                 res=0;
  61                 break;
  62         case 0x5f18:
  63         {
  64                 /*
  65                  * BL Bit[7:4]
  66                  * Memory Data Rate
  67                  * 0000: 66MHz
  68                  * 0001: 100MHz
  69                  * 0010: 133MHz
  70                  * 0011: 200MHz ( DDR200 )
  71                  * 0100: 266MHz ( DDR266 )
  72                  * 0101: 333MHz ( DDR333 )
  73                  * 0110: 400MHz ( DDR400 )
  74                  * 0111: 533MHz ( DDR I/II 533
  75                  * 1000: 667MHz ( DDR I/II 667)
  76                  * Bit[3:0]
  77                  * N:  Frame Buffer Size 2^N  MB
  78                  */
  79                 u8 i;
  80                 device_t dev;
  81                 dev = dev_find_slot(0, PCI_DEVFN(0, 3));
  82                 i = pci_read_config8(dev, 0xa1);
  83                 i = (i & 0x70);
  84                 i = i >> 4;
  85                 if (i == 0) {
  86                         regs->eax = 0x00;       //not support 5f18
  87                         break;
  88                 }
  89                 i = i + 2;
  90                 regs->ebx = (u32) i;
  91                 i = pci_read_config8(dev, 0x90);
  92                 i = (i & 0x07);
  93                 i = i + 3;
  94                 i = i << 4;
  95                 regs->ebx = regs->ebx + ((u32) i);
  96                 regs->eax = 0x5f;
  97                 res = 0;
  98                 break;
  99         }
 100         case 0x5f00:
 101                 regs->eax = 0x005f;
 102                 res = 0;
 103                 break;
 104         case 0x5f01:
 105                 regs->eax = 0x5f;
 106                 regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
 107                 res = 0;
 108                 break;
 109         case 0x5f02:
 110                 regs->eax=0x5f;
 111                 regs->ebx= (regs->ebx & 0xffff0000) | 2;
 112                 regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
 113                 regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
 114                 res=0;
 115                 break;
 116         case 0x5f0f:
 117                 regs->eax = 0x005f;
 118                 res = 0;
 119                 break;
 120         default:
 121                 printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
 122                                 regs->eax & 0xffff);
 123                 regs->eax = 0;
 124                 break;
 125         }
 126         return res;
 127 }
 128
 129 void write_protect_vgabios(void)
 130 {
 131         device_t dev;
 132
 133         printk(BIOS_INFO, "write_protect_vgabios\n");
 134         /* there are two possible devices. Just do both. */
 135         dev = dev_find_device(PCI_VENDOR_ID_VIA,
 136                               PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0);
 137         if (dev)
 138                 pci_write_config8(dev, 0x80, 0xff);
 139         /*vx855 no th 0x61 reg */
 140         /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0);
 141            //if(dev)
 142            //   pci_write_config8(dev, 0x61, 0xff); */
 143 }
 144
 145 extern u8 acpi_sleep_type;
 146 static void vga_init(device_t dev)
 147 {
 148         uint8_t reg8;
 149
 150         mainboard_interrupt_handlers(0x15, &via_vx800_int15_handler);
 151
 152         //A20 OPEN
 153         reg8 = inb(0x92);
 154         reg8 = reg8 | 2;
 155         outb(reg8, 0x92);
 156
 157         //*
 158         //pci_write_config8(dev, 0x04, 0x07);
 159         //pci_write_config32(dev,0x10, 0xa0000008);
 160         //pci_write_config32(dev,0x14, 0xdd000000);
 161         pci_write_config32(dev, 0x10, VIACONFIG_VGA_PCI_10);
 162         pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14);
 163         pci_write_config8(dev, 0x3c, 0x0a);     //same with vx855_lpc.c
 164         //*/
 165
 166         printk(BIOS_DEBUG, "Initializing VGA...\n");
 167
 168         pci_dev_init(dev);
 169
 170         printk(BIOS_DEBUG, "Enable VGA console\n");
 171         // this is how it should look:
 172         //   call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 173         // this is how it looks:
 174         vga_enable_console();
 175
 176         if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) {
 177                 /* It's not clear if these need to be programmed before or after
 178                  * the VGA bios runs. Try both, clean up later */
 179                 /* Set memory rate to 200MHz */
 180                 outb(0x3d, CRTM_INDEX);
 181                 reg8 = inb(CRTM_DATA);
 182                 reg8 &= 0x0f;
 183                 reg8 |= (0x3 << 4);
 184                 outb(0x3d, CRTM_INDEX);
 185                 outb(reg8, CRTM_DATA);
 186
 187 #if 0
 188                 /* Set framebuffer size to CONFIG_VIDEO_MB mb */
 189                 reg8 = (CONFIG_VIDEO_MB/4);
 190                 outb(0x39, SR_INDEX);
 191                 outb(reg8, SR_DATA);
 192 #endif
 193         }
 194 }
 195
 196 static struct device_operations vga_operations = {
 197         .read_resources = pci_dev_read_resources,
 198         .set_resources = pci_dev_set_resources,
 199         .enable_resources = pci_dev_enable_resources,
 200         .init = vga_init,
 201         .ops_pci = 0,
 202 };
 203
 204 static const struct pci_driver vga_driver __pci_driver = {
 205         .ops = &vga_operations,
 206         .vendor = PCI_VENDOR_ID_VIA,
 207         .device = PCI_DEVICE_ID_VIA_VX855_VGA,
 208 };