2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef ARCH_I386_PCI_RAWOPS_H
22 # define ARCH_I386_PCI_RAWOPS_H 1
25 #define PCI_RAWDEV(SEGBUS, DEV, FN) ( \
26 (((SEGBUS) & 0xFFF) << 20) | \
27 (((DEV) & 0x1F) << 15) | \
28 (((FN) & 0x07) << 12))
29 struct VIA_PCI_REG_INIT_TABLE {
39 typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
41 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
42 * We don't need to set %fs, and %gs anymore
43 * Before that We need to use %gs, and leave %fs to other RAM access
45 uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where)
48 #if PCI_IO_CFG_EXT == 0
49 addr = (dev>>4) | where;
51 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
53 outl(0x80000000 | (addr & ~3), 0xCF8);
54 return inb(0xCFC + (addr & 3));
58 uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
65 uint8_t pci_rawread_config8(device_t_raw dev, unsigned where)
68 return pci_mmio_rawread_config8(dev, where);
70 return pci_io_rawread_config8(dev, where);
74 uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where)
77 #if PCI_IO_CFG_EXT == 0
78 addr = (dev>>4) | where;
80 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
82 outl(0x80000000 | (addr & ~3), 0xCF8);
83 return inw(0xCFC + (addr & 2));
87 uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
95 uint16_t pci_rawread_config16(device_t_raw dev, unsigned where)
98 return pci_mmio_rawread_config16(dev, where);
100 return pci_io_rawread_config16(dev, where);
105 uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where)
108 #if PCI_IO_CFG_EXT == 0
109 addr = (dev>>4) | where;
111 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
113 outl(0x80000000 | (addr & ~3), 0xCF8);
118 uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
122 return read32x(addr);
126 uint32_t pci_rawread_config32(device_t_raw dev, unsigned where)
129 return pci_mmio_rawread_config32(dev, where);
131 return pci_io_rawread_config32(dev, where);
135 void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
138 #if PCI_IO_CFG_EXT == 0
139 addr = (dev>>4) | where;
141 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
143 outl(0x80000000 | (addr & ~3), 0xCF8);
144 outb(value, 0xCFC + (addr & 3));
148 void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
152 write8x(addr, value);
156 void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
159 pci_mmio_rawwrite_config8(dev, where, value);
161 pci_io_rawwrite_config8(dev, where, value);
166 void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
169 #if PCI_IO_CFG_EXT == 0
170 addr = (dev>>4) | where;
172 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
174 outl(0x80000000 | (addr & ~3), 0xCF8);
175 outw(value, 0xCFC + (addr & 2));
179 void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
183 write16x(addr, value);
187 void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
190 pci_mmio_rawwrite_config16(dev, where, value);
192 pci_io_rawwrite_config16(dev, where, value);
197 void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
200 #if PCI_IO_CFG_EXT == 0
201 addr = (dev>>4) | where;
203 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
205 outl(0x80000000 | (addr & ~3), 0xCF8);
210 void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
214 write32x(addr, value);
218 void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
221 pci_mmio_rawwrite_config32(dev, where, value);
223 pci_io_rawwrite_config32(dev, where, value);
228 void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask)
229 { u8 data=pci_rawread_config8(dev,where);
232 pci_rawwrite_config8(dev,where,data);
234 void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask)
235 { uint16_t data=pci_rawread_config16(dev,where);
238 pci_rawwrite_config16(dev,where,data);
240 void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask)
241 { uint32_t data=pci_rawread_config32(dev,where);
244 pci_rawwrite_config32(dev,where,data);
247 void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask)
255 void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata)
258 device_t_raw devbxdxfx;
260 if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0))
262 if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){
263 devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function);
264 pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask);