src/northbridge/via/vt8623/vga.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/io.h>
  22 #include <stdint.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <bitops.h>
  29 #include <cpu/cpu.h>
  30 #include <cpu/x86/mtrr.h>
  31 #include <cpu/x86/msr.h>
  32 #include <arch/interrupt.h>
  33 #include "chip.h"
  34 #include "northbridge.h"
  35
  36 static int via_vt8623_int15_handler(struct eregs *regs)
  37 {
  38         int res=-1;
  39         printk(BIOS_DEBUG, "via_vt8623_int15_handler\n");
  40         switch(regs->eax & 0xffff) {
  41         case 0x5f19:
  42                 break;
  43         case 0x5f18:
  44                 regs->eax=0x5f;
  45                 regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
  46                 regs->ecx=0x060;
  47                 res=0;
  48                 break;
  49         case 0x5f00:
  50                 regs->eax = 0x8600;
  51                 break;
  52         case 0x5f01:
  53                 regs->eax = 0x5f;
  54                 regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
  55                 res = 0;
  56                 break;
  57         case 0x5f02:
  58                 regs->eax=0x5f;
  59                 regs->ebx= (regs->ebx & 0xffff0000) | 2;
  60                 regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
  61                 regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
  62                 res=0;
  63                 break;
  64         case 0x5f0f:
  65                 regs->eax=0x860f;
  66                 break;
  67         default:
  68                 printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
  69                                 regs->eax & 0xffff);
  70                 break;
  71         }
  72         return res;
  73 }
  74
  75 void write_protect_vgabios(void)
  76 {
  77         device_t dev;
  78
  79         printk(BIOS_DEBUG, "write_protect_vgabios\n");
  80
  81         dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  82         if (dev)
  83                 pci_write_config8(dev, 0x61, 0xaa);
  84
  85         dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
  86         if (dev)
  87                 pci_write_config8(dev, 0x61, 0xaa);
  88 }
  89
  90 static void vga_random_fixup(device_t dev)
  91 {
  92         printk(BIOS_DEBUG, "VGA random fixup ...\n");
  93         pci_write_config8(dev, 0x04, 0x07);
  94         pci_write_config8(dev, 0x0d, 0x20);
  95         pci_write_config32(dev,0x10,0xd8000008);
  96         pci_write_config32(dev,0x14,0xdc000000);
  97 }
  98
  99 static void vga_init(device_t dev)
 100 {
 101         vga_random_fixup(dev);
 102
 103         mainboard_interrupt_handlers(0x15, &via_vt8623_int15_handler);
 104
 105 #ifdef MEASURE_VGA_INIT_TIME
 106         msr_t clocks1, clocks2, instructions, setup;
 107
 108         // set up performnce counters for debugging vga init sequence
 109         setup.lo = 0x1c0; // count instructions
 110         wrmsr(0x187,setup);
 111         instructions.hi = 0;
 112         instructions.lo = 0;
 113         wrmsr(0xc2,instructions);
 114         clocks1 = rdmsr(0x10);
 115 #endif
 116         printk(BIOS_DEBUG, "Initializing VGA...\n");
 117
 118         pci_dev_init(dev);
 119
 120         printk(BIOS_DEBUG, "Enable VGA console\n");
 121         // this is how it should look:
 122         //   call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 123         // this is how it looks:
 124         vga_enable_console();
 125
 126 #ifdef MEASURE_VGA_INIT_TIME
 127         clocks2 = rdmsr(0x10);
 128         instructions = rdmsr(0xc2);
 129
 130         printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 131         printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 132         printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 133 #endif
 134
 135         pci_write_config32(dev, 0x30, 0);
 136
 137 #if 0
 138         /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
 139         unsigned long fb;
 140         add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
 141         fb = pci_read_config32(dev,0x10); // get the fb address
 142         add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
 143 #endif
 144 }
 145
 146 static struct device_operations vga_operations = {
 147         .read_resources = pci_dev_read_resources,
 148         .set_resources = pci_dev_set_resources,
 149         .enable_resources = pci_dev_enable_resources,
 150         .init = vga_init,
 151         .ops_pci = 0,
 152 };
 153
 154 static const struct pci_driver vga_driver __pci_driver = {
 155         .ops = &vga_operations,
 156         .vendor = PCI_VENDOR_ID_VIA,
 157         .device = 0x3122,
 158 };