2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 Automatically detect and set up ddr dram on the CLE266 chipset.
23 Assumes DDR memory, though chipset also supports SDRAM
24 Assumes at least 266Mhz memory as no attempt is made to clock
25 the chipset down if slower memory is installed.
27 256 Mb 266Mhz 1 Bank (i.e. single sided)
28 256 Mb 266Mhz 2 Bank (i.e. double sided)
29 512 Mb 266Mhz 2 Bank (i.e. double sided)
31 /* ported and enhanced from assembler level code in coreboot v1 */
33 #include <cpu/x86/mtrr.h>
38 void dimm_read(unsigned long bank,unsigned long x)
41 volatile unsigned long y;
43 y = * (volatile unsigned long *) (x+ bank) ;
49 dumpnorth(device_t north)
52 for(r = 0; r < 256; r += 16) {
55 for(c = 0; c < 16; c++) {
56 print_debug_hex8(pci_read_config8(north, r+c));
62 void print_val(char *str, int val)
65 print_debug_hex8(val);
68 static void ddr_ram_setup(const struct mem_controller *ctrl)
70 device_t north = (device_t) 0;
73 unsigned long bank_address;
75 print_debug("vt8623 init starting\n");
76 north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
80 pci_write_config8(north,0x75,0x08);
83 pci_write_config8(north,0x50,0xc8);
84 pci_write_config8(north,0x51,0xde);
85 pci_write_config8(north,0x52,0xcf);
86 pci_write_config8(north,0x53,0x88);
87 pci_write_config8(north,0x55,0x04);
90 DRAM MA Map Type Device 0 Offset 58
92 Determine memory addressing based on the module's memory technology and
93 arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
95 Bank 1/0 MA map type 58[7-5]
96 Bank 1/0 command rate 58[4]
97 Bank 3/2 MA map type 58[3-1]
98 Bank 3/2 command rate 58[0]
101 Read SPD byte 17, Number of banks on SDRAM device.
104 b = smbus_read_byte(0xa0,17);
105 print_val("Detecting Memory\nNumber of Banks ",b);
107 if( b != 2 ){ // not 16 Mb type
110 Read SPD byte 3, Number of row addresses.
112 b = smbus_read_byte(0xa0,3);
113 print_val("\nNumber of Rows ",b);
114 if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
117 Read SPD byte 13, Primary DRAM width.
119 b = smbus_read_byte(0xa0,13);
120 print_val("\nPriamry DRAM width",b);
121 if( b != 4 ) // mot 64/128Mb (x4)
128 Read SPD byte 4, Number of column addresses.
130 b = smbus_read_byte(0xa0,4);
131 print_val("\nNo Columns ",b);
132 if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
133 if( b == 9 ) c |= 0x40; // 9 bit col addr
134 if( b == 8 ) c |= 0x20; // 8 bit col addr
137 print_val("\nMA type ",c);
138 pci_write_config8(north,0x58,c);
141 DRAM bank size. See 4.3.1 pg 35
143 5a->5d set to end address for each bank. 1 bit == 16MB
146 5c = bank 0 + b1 + b2
147 5d = bank 0 + b1 + b2 + b3
150 // Read SPD byte 31 Module bank density
152 b = smbus_read_byte(0xa0,31);
153 if( b & 0x02 ) c = 0x80; // 2GB
154 else if( b & 0x01) c = 0x40; // 1GB
155 else if( b & 0x80) c = 0x20; // 512Mb
156 else if( b & 0x40) c = 0x10; // 256Mb
157 else if( b & 0x20) c = 0x08; // 128Mb
158 else if( b & 0x10) c = 0x04; // 64Mb
159 else if( b & 0x08) c = 0x02; // 32Mb
160 else if( b & 0x04) c = 0x01; // 16Mb / 4Gb
161 else c = 0x01; // Error, use default
164 print_val("\nBank 0 (*16 Mb) ",c);
166 // set bank zero size
167 pci_write_config8(north,0x5a,c);
168 // SPD byte 5 # of physical banks
169 b = smbus_read_byte(0xa0,5);
171 print_val("\nNo Physical Banks ",b);
175 print_val("\nTotal Memory (*16 Mb) ",c);
177 pci_write_config8(north,0x5b,c);
178 pci_write_config8(north,0x5c,c);
179 pci_write_config8(north,0x5d,c);
182 /* Read SPD byte 18 CAS Latency */
183 b = smbus_read_byte(0xa0,18);
184 print_debug("\nCAS Supported ");
191 print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
192 print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
193 print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
196 if( b & 0x10 ){ // DDR offering optional CAS 3
197 print_debug("\nStarting at CAS 3");
199 /* see if we can better it */
200 if( b & 0x08 ){ // DDR mandatory CAS 2.5
201 if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
202 print_debug("\nWe can do CAS 2.5");
206 if( b & 0x04 ){ // DDR mandatory CAS 2
207 if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
208 print_debug("\nWe can do CAS 2");
212 }else{ // no optional CAS values just 2 & 2.5
213 print_debug("\nStarting at CAS 2.5");
214 c = 0x20; // assume CAS 2.5
215 if( b & 0x04){ // Should always happen
216 if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
217 print_debug("\nWe can do CAS 2");
226 DRAM Timing Device 0 Offset 64
229 RAS Pulse width 64[6]
239 Bank Interleave 64[1,0]
242 Determine row pre-charge time (tRP)
253 Read SPD byte 27, min row pre-charge time.
256 b = smbus_read_byte(0xa0,27);
257 print_val("\ntRP ",b);
258 if( b > 0x3c ) // set tRP = 3T
263 Determine RAS to CAS delay (tRCD)
265 Read SPD byte 29, min row pre-charge time.
268 b = smbus_read_byte(0xa0,29);
269 print_val("\ntRCD ",b);
270 if( b > 0x3c ) // set tRCD = 3T
274 Determine RAS pulse width (tRAS)
277 Read SPD byte 30, device min active to pre-charge time.
280 b = smbus_read_byte(0xa0,30);
281 print_val("\ntRAS ",b);
282 if( b > 0x25 ) // set tRAS = 6T
287 Determine bank interleave
289 Read SPD byte 17, Number of banks on SDRAM device.
291 b = smbus_read_byte(0xa0,17);
292 if( b == 4) c |= 0x02;
293 else if (b == 2) c |= 0x01;
296 /* set DRAM timing for all banks */
297 pci_write_config8(north,0x64,c);
299 /* set DRAM type to DDR */
300 pci_write_config8(north,0x60,0x02);
303 /* DRAM arbitration timer */
304 pci_write_config8(north,0x65,0x32);
308 CPU Frequency Device 0 Offset 54
310 CPU Frequency 54[7,6] bootstraps at 0xc0 (133Mhz)
311 DRAM burst length = 8 54[5]
313 pci_write_config8(north,0x54,0xe0);
317 DRAM Clock Device 0 Offset 69
319 DRAM/CPU speed 69[7,6] (leave at default 00 == CPU)
320 Controller que > 2 69[5]
321 Controller que != 4 69[4]
322 DRAM 8k page size 69[3]
323 DRAM 4k page size 69[2]
324 Multiple page mode 69[0]
327 pci_write_config8(north,0x69,0x2d);
329 /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
334 pci_write_config8(north,0x6b,0x10);
337 /* Disable DRAM refresh */
338 pci_write_config8(north,0x6a,0x0);
341 /* Set drive for 1 bank DDR (Table 4.4.2, pg 40) */
342 pci_write_config8(north,0x6d,0x044);
343 pci_write_config8(north,0x67,0x3a);
345 b = smbus_read_byte(0xa0,5); // SPD byte 5 # of physical banks
347 // Increase drive control when there is more than 1 physical bank
348 pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE
349 pci_write_config8(north,0x6d,0x55); // DC: Early clock select, DQM, CS#, MD
351 /* place frame buffer on last bank */
352 if( !b) b++; // make sure at least 1 bank reported
353 pci_write_config8(north,0xe3,b-1);
355 for( bank = 0 , bank_address=0; bank < b ; bank++){
357 DDR init described in Via BIOS Porting Guide. Pg 28 (4.2.3.1)
361 /* NOP command enable */
362 pci_write_config8(north,0x6b,0x11);
364 /* read a double word from any address of the dimm */
365 dimm_read(bank_address,0x1f000);
368 /* All bank precharge Command Enable */
369 pci_write_config8(north,0x6b,0x12);
370 dimm_read(bank_address,0x1f000);
374 pci_write_config8(north,0x6b,0x13);
375 dimm_read(bank_address,0x2000);
377 dimm_read(bank_address,0x800);
380 /* All banks precharge Command Enable */
381 pci_write_config8(north,0x6b,0x12);
382 dimm_read(bank_address,0x1f200);
384 /* CBR Cycle Enable */
385 pci_write_config8(north,0x6b,0x14);
388 dimm_read(bank_address,0x1f300);
390 dimm_read(bank_address,0x1f400);
392 dimm_read(bank_address,0x1f500);
394 dimm_read(bank_address,0x1f600);
396 dimm_read(bank_address,0x1f700);
398 dimm_read(bank_address,0x1f800);
400 dimm_read(bank_address,0x1f900);
402 dimm_read(bank_address,0x1fa00);
406 pci_write_config8(north,0x6b,0x13);
409 Mode Register Definition
410 with adjustement so that address calculation is correct - 64 bit technology, therefore
411 a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
412 to DIMM as a row or column address.
415 MR[6] Burst Type 0 = sequential, 1 = interleaved
416 MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
429 CAS 2 0101011000 = 0x158
430 CAS 2.5 1101011000 = 0x358
431 CAS 3 0111011000 = 0x1d8
434 c = pci_read_config8(north,0x64);
435 if( (c & 0x30) == 0x10 )
436 dimm_read(bank_address,0x150);
437 else if((c & 0x30) == 0x20 )
438 dimm_read(bank_address,0x350);
440 dimm_read(bank_address,0x1d0);
442 //dimm_read(bank_address,0x350);
444 /* Normal SDRAM Mode */
445 pci_write_config8(north,0x6b,0x58 );
448 bank_address = pci_read_config8(north,0x5a+bank) * 0x1000000;
449 } // end of for each bank
451 /* Adjust DQS (data strobe output delay). See 4.2.3.2 pg 29 */
452 pci_write_config8(north,0x66,0x41);
454 /* determine low bond */
456 bank_address = pci_read_config8(north,0x5a) * 0x1000000;
460 for(i = 0 ; i < 0x0ff; i++){
461 c = i ^ (i>>1); // convert to gray code
462 pci_write_config8(north,0x68,c);
464 *(volatile unsigned long*)(0x4000) = 0;
465 *(volatile unsigned long*)(0x4100+bank_address) = 0;
466 *(volatile unsigned long*)(0x4200) = 0;
467 *(volatile unsigned long*)(0x4300+bank_address) = 0;
468 *(volatile unsigned long*)(0x4400) = 0;
469 *(volatile unsigned long*)(0x4500+bank_address) = 0;
473 *(volatile unsigned long*)(0x4000) = 0x12345678;
474 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
475 *(volatile unsigned long*)(0x4200) = 0x78123456;
476 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
477 *(volatile unsigned long*)(0x4400) = 0x56781234;
478 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
481 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
484 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
487 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
490 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
493 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
496 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
499 // if everything verified then found low bond
503 print_val("\nLow Bond ",i);
506 for( ; i <0xff ; i++){
507 pci_write_config8(north,0x68,i ^ (i>>1) );
510 *(volatile unsigned long*)(0x8000) = 0;
511 *(volatile unsigned long*)(0x8100+bank_address) = 0;
512 *(volatile unsigned long*)(0x8200) = 0x0;
513 *(volatile unsigned long*)(0x8300+bank_address) = 0;
514 *(volatile unsigned long*)(0x8400) = 0x0;
515 *(volatile unsigned long*)(0x8500+bank_address) = 0;
518 *(volatile unsigned long*)(0x8000) = 0x12345678;
519 *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
520 *(volatile unsigned long*)(0x8200) = 0x78123456;
521 *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
522 *(volatile unsigned long*)(0x8400) = 0x56781234;
523 *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
526 if( *(volatile unsigned long*)(0x8000) != 0x12345678)
529 if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
532 if( *(volatile unsigned long*)(0x8200) != 0x78123456)
535 if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
538 if( *(volatile unsigned long*)(0x8400) != 0x56781234)
541 if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
545 print_val(" High Bond",i);
546 c = ((i - c)<<1)/3 +c;
547 print_val(" Setting DQS delay",c);
548 c = c ^ (c>>1); // convert to gray code
549 pci_write_config8(north,0x68,c);
550 pci_write_config8(north,0x68,0x42);
552 print_debug("Unable to determine low bond - Setting default\n");
553 pci_write_config8(north,0x68,0x59);
557 pci_write_config8(north,0x66,0x01);
558 pci_write_config8(north,0x55,0x07);
563 DRAM refresh rate Device 0 Offset 6a
565 Units of 16 DRAM clock cycles. (See 4.4.1 pg 39)
567 Rx69 (DRAM freq) Rx58 (chip tech) Rx6a
570 133Mhz 256/512Mb 0x43
572 100Mhz 256/512Mb 0x32
575 b = pci_read_config8(north,0x58);
576 if( b < 0x80 ) // 256 tech
577 pci_write_config8(north,0x6a,0x86);
579 pci_write_config8(north,0x6a,0x43);
581 pci_write_config8(north,0x61,0xff);
582 //pci_write_config8(north,0x67,0x22);
585 pci_write_config8(north,0x70,0x82);
586 pci_write_config8(north,0x73,0x01);
587 pci_write_config8(north,0x76,0x50);
590 pci_write_config8(north,0x71,0xc8);
593 /* graphics aperture base */
595 pci_write_config8(north,0x13,0xd0);
597 //pci_write_config8(north,0xe1,0xdf);
598 //pci_write_config8(north,0xe2,0x42);
599 pci_write_config8(north,0xe0,0x00);
601 pci_write_config8(north,0x84,0x80);
602 pci_write_config16(north,0x80,0x610f);
603 pci_write_config32(north,0x88,0x00000002);
607 pci_write_config8(north,0xa8,0x04);
608 pci_write_config8(north,0xac,0x2f);
609 pci_write_config8(north,0xae,0x04);
611 print_debug("vt8623 done\n");
614 print_debug("AGP\n");
615 north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
616 pci_write_config32(north,0x20,0xddf0dc00);
617 pci_write_config32(north,0x24,0xdbf0d800);
618 pci_write_config8(north,0x3e,0x0c);
621 //print_err("VGA\n");
622 //north = pci_locate_device(PCI_ID(0x1106, 0x3122), 0);
623 //pci_write_config32(north,0x10,0xd8000008);
624 //pci_write_config32(north,0x14,0xdc000000);