src/northbridge/via/vt8623/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19  */
  20
  21 /*
  22   Automatically detect and set up ddr dram on the CLE266 chipset.
  23   Assumes DDR memory, though chipset also supports SDRAM
  24   Assumes at least 266Mhz memory as no attempt is made to clock
  25   the chipset down if slower memory is installed.
  26   So far tested on:
  27         256 Mb 266Mhz 1 Bank (i.e. single sided)
  28         256 Mb 266Mhz 2 Bank (i.e. double sided)
  29         512 Mb 266Mhz 2 Bank (i.e. double sided)
  30 */
  31 /* ported and enhanced from assembler level code in coreboot v1 */
  32
  33 #include <cpu/x86/mtrr.h>
  34 #include "raminit.h"
  35
  36
  37
  38 void dimm_read(unsigned long bank,unsigned long x)
  39 {
  40         //unsigned long eax;
  41         volatile unsigned long y;
  42         //eax =  x;
  43         y = * (volatile unsigned long *) (x+ bank) ;
  44
  45 }
  46
  47
  48 void
  49 dumpnorth(device_t north)
  50 {
  51         uint16_t r, c;
  52         for(r = 0; r < 256; r += 16) {
  53                 print_debug_hex8(r);
  54                 print_debug(":");
  55                 for(c = 0; c < 16; c++) {
  56                         print_debug_hex8(pci_read_config8(north, r+c));
  57                         print_debug(" ");
  58                 }
  59                 print_debug("\n");
  60   }
  61 }
  62 void print_val(char *str, int val)
  63 {
  64         print_debug(str);
  65         print_debug_hex8(val);
  66 }
  67
  68 static void ddr_ram_setup(const struct mem_controller *ctrl)
  69 {
  70         device_t north = (device_t) 0;
  71         uint8_t b, c, bank;
  72         uint16_t i;
  73         unsigned long bank_address;
  74
  75         print_debug("vt8623 init starting\n");
  76         north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
  77         north = 0;
  78
  79
  80         pci_write_config8(north,0x75,0x08);
  81
  82         /* setup cpu */
  83         pci_write_config8(north,0x50,0xc8);
  84         pci_write_config8(north,0x51,0xde);
  85         pci_write_config8(north,0x52,0xcf);
  86         pci_write_config8(north,0x53,0x88);
  87         pci_write_config8(north,0x55,0x04);
  88
  89 /*
  90     DRAM MA Map Type  Device 0  Offset 58
  91
  92     Determine memory addressing based on the module's memory technology and
  93     arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
  94
  95     Bank 1/0 MA map type   58[7-5]
  96     Bank 1/0 command rate  58[4]
  97     Bank 3/2 MA map type   58[3-1]
  98     Bank 3/2 command rate  58[0]
  99
 100
 101     Read SPD byte 17, Number of banks on SDRAM device.
 102 */
 103         c = 0;
 104         b = smbus_read_byte(0xa0,17);
 105         print_val("Detecting Memory\nNumber of Banks ",b);
 106
 107         if( b != 2 ){            // not 16 Mb type
 108
 109 /*
 110     Read SPD byte 3, Number of row addresses.
 111 */
 112                 b = smbus_read_byte(0xa0,3);
 113                 print_val("\nNumber of Rows ",b);
 114                 if( b >= 0x0d ){        // not 64/128Mb (rows <=12)
 115
 116 /*
 117     Read SPD byte 13, Primary DRAM width.
 118 */
 119                         b = smbus_read_byte(0xa0,13);
 120                         print_val("\nPriamry DRAM width",b);
 121                         if( b != 4 )   // mot 64/128Mb (x4)
 122                                 c = 0x80;  // 256Mb
 123                 }
 124
 125 /*
 126     64/128Mb chip
 127
 128     Read SPD byte 4, Number of column addresses.
 129 */
 130                 b = smbus_read_byte(0xa0,4);
 131                 print_val("\nNo Columns ",b);
 132                 if( b == 10 || b == 11 ) c |= 0x60;   // 10/11 bit col addr
 133                 if( b == 9 ) c |= 0x40;           // 9 bit col addr
 134                 if( b == 8 ) c |= 0x20;           // 8 bit col addr
 135
 136         }
 137         print_val("\nMA type ",c);
 138         pci_write_config8(north,0x58,c);
 139
 140 /*
 141     DRAM bank size.  See 4.3.1 pg 35
 142
 143     5a->5d  set to end address for each bank.  1 bit == 16MB
 144     5a = bank 0
 145     5b = bank 0 + b1
 146     5c = bank 0 + b1 + b2
 147     5d = bank 0 + b1 + b2 + b3
 148 */
 149
 150 // Read SPD byte 31 Module bank density
 151         c = 0;
 152         b = smbus_read_byte(0xa0,31);
 153         if( b & 0x02 ) c = 0x80;         // 2GB
 154         else if( b & 0x01) c = 0x40;     // 1GB
 155         else if( b & 0x80) c = 0x20;     // 512Mb
 156         else if( b & 0x40) c = 0x10;     // 256Mb
 157         else if( b & 0x20) c = 0x08;     // 128Mb
 158         else if( b & 0x10) c = 0x04;     // 64Mb
 159         else if( b & 0x08) c = 0x02;     // 32Mb
 160         else if( b & 0x04) c = 0x01;     // 16Mb / 4Gb
 161         else c = 0x01;                   // Error, use default
 162
 163
 164         print_val("\nBank 0 (*16 Mb) ",c);
 165
 166         // set bank zero size
 167         pci_write_config8(north,0x5a,c);
 168         // SPD byte 5  # of physical banks
 169         b = smbus_read_byte(0xa0,5);
 170
 171         print_val("\nNo Physical Banks ",b);
 172         if( b == 2)
 173                 c <<=1;
 174
 175         print_val("\nTotal Memory (*16 Mb) ",c);
 176         // set banks 1,2,3
 177         pci_write_config8(north,0x5b,c);
 178         pci_write_config8(north,0x5c,c);
 179         pci_write_config8(north,0x5d,c);
 180
 181
 182         /* Read SPD byte 18 CAS Latency */
 183         b = smbus_read_byte(0xa0,18);
 184         print_debug("\nCAS Supported ");
 185         if(b & 0x04)
 186                 print_debug("2 ");
 187         if(b & 0x08)
 188                 print_debug("2.5 ");
 189         if(b & 0x10)
 190                 print_debug("3");
 191         print_val("\nCycle time at CL X     (nS)",smbus_read_byte(0xa0,9));
 192         print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
 193         print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(0xa0,25));
 194
 195
 196         if( b & 0x10 ){             // DDR offering optional CAS 3
 197                 print_debug("\nStarting at CAS 3");
 198                 c = 0x30;
 199                 /* see if we can better it */
 200                 if( b & 0x08 ){     // DDR mandatory CAS 2.5
 201                         if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
 202                                 print_debug("\nWe can do CAS 2.5");
 203                                 c = 0x20;
 204                         }
 205                 }
 206                 if( b & 0x04 ){     // DDR mandatory CAS 2
 207                         if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
 208                                 print_debug("\nWe can do CAS 2");
 209                                 c = 0x10;
 210                         }
 211                 }
 212         }else{                     // no optional CAS values just 2 & 2.5
 213                 print_debug("\nStarting at CAS 2.5");
 214                 c = 0x20;          // assume CAS 2.5
 215                 if( b & 0x04){      // Should always happen
 216                         if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
 217                                 print_debug("\nWe can do CAS 2");
 218                                 c = 0x10;
 219                         }
 220                 }
 221         }
 222
 223
 224
 225 /*
 226     DRAM Timing  Device 0  Offset 64
 227
 228     Row pre-charge  64[7]
 229     RAS Pulse width 64[6]
 230     CAS Latency     64[5,4]
 231
 232          SDR  DDR
 233       00  1T   -
 234       01  2T   2T
 235       10  3T   2.5T
 236       11  -    3T
 237
 238     RAS/CAS delay   64[2]
 239     Bank Interleave 64[1,0]
 240
 241
 242     Determine row pre-charge time (tRP)
 243
 244     T    nS    SPD*4   SPD
 245     1T   7.5   0x1e
 246     2T   15    0x3c
 247     3T   22.5  0x5a
 248     4T   30            0x1e
 249     5T   37.5          0x25 .5?
 250     6T   45            0x2d
 251
 252
 253     Read SPD byte 27, min row pre-charge time.
 254 */
 255
 256         b = smbus_read_byte(0xa0,27);
 257         print_val("\ntRP ",b);
 258         if( b > 0x3c )           // set tRP = 3T
 259                 c |= 0x80;
 260
 261
 262 /*
 263     Determine RAS to CAS delay (tRCD)
 264
 265     Read SPD byte 29, min row pre-charge time.
 266 */
 267
 268         b = smbus_read_byte(0xa0,29);
 269         print_val("\ntRCD ",b);
 270         if( b > 0x3c )           // set tRCD = 3T
 271                 c |= 0x04;
 272
 273 /*
 274     Determine RAS pulse width (tRAS)
 275
 276
 277     Read SPD byte 30, device min active to pre-charge time.
 278 */
 279
 280         b = smbus_read_byte(0xa0,30);
 281         print_val("\ntRAS ",b);
 282         if( b > 0x25 )           // set tRAS = 6T
 283                 c |= 0x40;
 284
 285
 286 /*
 287     Determine bank interleave
 288
 289     Read SPD byte 17, Number of banks on SDRAM device.
 290 */
 291         b = smbus_read_byte(0xa0,17);
 292         if( b == 4) c |= 0x02;
 293         else if (b == 2) c |= 0x01;
 294
 295
 296         /* set DRAM timing for all banks */
 297         pci_write_config8(north,0x64,c);
 298
 299         /* set DRAM type to DDR */
 300         pci_write_config8(north,0x60,0x02);
 301
 302
 303         /* DRAM arbitration timer */
 304         pci_write_config8(north,0x65,0x32);
 305
 306
 307 /*
 308     CPU Frequency  Device 0 Offset 54
 309
 310     CPU Frequency          54[7,6]  bootstraps at 0xc0 (133Mhz)
 311     DRAM burst length = 8  54[5]
 312 */
 313         pci_write_config8(north,0x54,0xe0);
 314
 315
 316 /*
 317     DRAM Clock  Device 0 Offset 69
 318
 319     DRAM/CPU speed      69[7,6]  (leave at default 00 == CPU)
 320     Controller que > 2  69[5]
 321     Controller que != 4 69[4]
 322     DRAM 8k page size   69[3]
 323     DRAM 4k page size   69[2]
 324     Multiple page mode  69[0]
 325 */
 326
 327         pci_write_config8(north,0x69,0x2d);
 328
 329         /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
 330         udelay(200);
 331
 332
 333         /* Enable CKE */
 334         pci_write_config8(north,0x6b,0x10);
 335         udelay(200);
 336
 337         /* Disable DRAM refresh */
 338         pci_write_config8(north,0x6a,0x0);
 339
 340
 341         /* Set drive for 1 bank DDR  (Table 4.4.2, pg 40) */
 342         pci_write_config8(north,0x6d,0x044);
 343         pci_write_config8(north,0x67,0x3a);
 344
 345         b = smbus_read_byte(0xa0,5); // SPD byte 5  # of physical banks
 346         if( b > 1) {
 347                 // Increase drive control when there is more than 1 physical bank
 348                 pci_write_config8(north,0x6c,0x84);   // Drive control: MA, DQS, MD/CKE
 349                 pci_write_config8(north,0x6d,0x55);   // DC: Early clock select, DQM, CS#, MD
 350         }
 351         /* place frame buffer on last bank */
 352         if( !b) b++;     // make sure at least 1 bank reported
 353         pci_write_config8(north,0xe3,b-1);
 354
 355         for( bank = 0 , bank_address=0; bank < b ; bank++){
 356 /*
 357     DDR init described in Via BIOS Porting Guide.  Pg 28 (4.2.3.1)
 358 */
 359
 360
 361                 /* NOP command enable */
 362                 pci_write_config8(north,0x6b,0x11);
 363
 364                 /* read a double word from any address of the dimm */
 365                 dimm_read(bank_address,0x1f000);
 366                 //udelay(200);
 367
 368                 /* All bank precharge Command Enable */
 369                 pci_write_config8(north,0x6b,0x12);
 370                 dimm_read(bank_address,0x1f000);
 371
 372
 373                 /* MSR Enable */
 374                 pci_write_config8(north,0x6b,0x13);
 375                 dimm_read(bank_address,0x2000);
 376                 udelay(1);
 377                 dimm_read(bank_address,0x800);
 378                 udelay(1);
 379
 380                 /* All banks precharge Command Enable */
 381                 pci_write_config8(north,0x6b,0x12);
 382                 dimm_read(bank_address,0x1f200);
 383
 384                 /* CBR Cycle Enable */
 385                 pci_write_config8(north,0x6b,0x14);
 386
 387                 /* Read 8 times */
 388                 dimm_read(bank_address,0x1f300);
 389                 udelay(100);
 390                 dimm_read(bank_address,0x1f400);
 391                 udelay(100);
 392                 dimm_read(bank_address,0x1f500);
 393                 udelay(100);
 394                 dimm_read(bank_address,0x1f600);
 395                 udelay(100);
 396                 dimm_read(bank_address,0x1f700);
 397                 udelay(100);
 398                 dimm_read(bank_address,0x1f800);
 399                 udelay(100);
 400                 dimm_read(bank_address,0x1f900);
 401                 udelay(100);
 402                 dimm_read(bank_address,0x1fa00);
 403                 udelay(100);
 404
 405                 /* MSR Enable */
 406                 pci_write_config8(north,0x6b,0x13);
 407
 408 /*
 409     Mode Register Definition
 410     with adjustement so that address calculation is correct - 64 bit technology, therefore
 411     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
 412     to DIMM as a row or column address.
 413
 414     MR[9-7]   CAS Latency
 415     MR[6]     Burst Type 0 = sequential, 1 = interleaved
 416     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
 417     MR[0-2]   dont care
 418
 419     CAS Latency
 420     000       reserved
 421     001       reserved
 422     010       2
 423     011       3
 424     100       reserved
 425     101       1.5
 426     110       2.5
 427     111       reserved
 428
 429     CAS 2     0101011000 = 0x158
 430     CAS 2.5   1101011000 = 0x358
 431     CAS 3     0111011000 = 0x1d8
 432
 433 */
 434                 c = pci_read_config8(north,0x64);
 435                 if( (c & 0x30) == 0x10 )
 436                         dimm_read(bank_address,0x150);
 437                 else if((c & 0x30) == 0x20 )
 438                         dimm_read(bank_address,0x350);
 439                 else
 440                         dimm_read(bank_address,0x1d0);
 441
 442                 //dimm_read(bank_address,0x350);
 443
 444                 /* Normal SDRAM Mode */
 445                 pci_write_config8(north,0x6b,0x58 );
 446
 447
 448                 bank_address = pci_read_config8(north,0x5a+bank) * 0x1000000;
 449         } // end of for each bank
 450
 451         /* Adjust DQS (data strobe output delay). See 4.2.3.2 pg 29 */
 452         pci_write_config8(north,0x66,0x41);
 453
 454         /* determine low bond */
 455         if( b == 2)
 456                 bank_address = pci_read_config8(north,0x5a) * 0x1000000;
 457         else
 458                 bank_address = 0;
 459
 460         for(i = 0 ; i < 0x0ff; i++){
 461                 c = i ^ (i>>1);                 // convert to gray code
 462                 pci_write_config8(north,0x68,c);
 463                 // clear
 464                 *(volatile unsigned long*)(0x4000) = 0;
 465                 *(volatile unsigned long*)(0x4100+bank_address) = 0;
 466                 *(volatile unsigned long*)(0x4200) = 0;
 467                 *(volatile unsigned long*)(0x4300+bank_address) = 0;
 468                 *(volatile unsigned long*)(0x4400) = 0;
 469                 *(volatile unsigned long*)(0x4500+bank_address) = 0;
 470
 471
 472                 // fill
 473                 *(volatile unsigned long*)(0x4000) = 0x12345678;
 474                 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
 475                 *(volatile unsigned long*)(0x4200) = 0x78123456;
 476                 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
 477                 *(volatile unsigned long*)(0x4400) = 0x56781234;
 478                 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
 479
 480                         // verify
 481                 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
 482                         continue;
 483
 484                 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
 485                         continue;
 486
 487                 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
 488                         continue;
 489
 490                 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
 491                         continue;
 492
 493                 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
 494                         continue;
 495
 496                 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
 497                         continue;
 498
 499                 // if everything verified then found low bond
 500                 break;
 501
 502         }
 503         print_val("\nLow Bond ",i);
 504         if( i < 0xff ){
 505                 c = i++;
 506                 for(  ; i <0xff ; i++){
 507                         pci_write_config8(north,0x68,i ^ (i>>1) );
 508
 509                         // clear
 510                         *(volatile unsigned long*)(0x8000) = 0;
 511                         *(volatile unsigned long*)(0x8100+bank_address) = 0;
 512                         *(volatile unsigned long*)(0x8200) = 0x0;
 513                         *(volatile unsigned long*)(0x8300+bank_address) = 0;
 514                         *(volatile unsigned long*)(0x8400) = 0x0;
 515                         *(volatile unsigned long*)(0x8500+bank_address) = 0;
 516
 517                         // fill
 518                         *(volatile unsigned long*)(0x8000) = 0x12345678;
 519                         *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
 520                         *(volatile unsigned long*)(0x8200) = 0x78123456;
 521                         *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
 522                         *(volatile unsigned long*)(0x8400) = 0x56781234;
 523                         *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
 524
 525                         // verify
 526                         if( *(volatile unsigned long*)(0x8000) != 0x12345678)
 527                                 break;
 528
 529                         if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
 530                                 break;
 531
 532                         if( *(volatile unsigned long*)(0x8200) != 0x78123456)
 533                                 break;
 534
 535                         if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
 536                                 break;
 537
 538                         if( *(volatile unsigned long*)(0x8400) != 0x56781234)
 539                                 break;
 540
 541                         if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
 542                                 break;
 543
 544                 }
 545                 print_val("  High Bond",i);
 546                 c = ((i - c)<<1)/3 +c;
 547                 print_val("  Setting DQS delay",c);
 548                 c = c ^ (c>>1);         // convert to gray code
 549                 pci_write_config8(north,0x68,c);
 550                 pci_write_config8(north,0x68,0x42);
 551         }else{
 552                 print_debug("Unable to determine low bond - Setting default\n");
 553                 pci_write_config8(north,0x68,0x59);
 554         }
 555
 556
 557         pci_write_config8(north,0x66,0x01);
 558         pci_write_config8(north,0x55,0x07);
 559
 560
 561
 562 /*
 563     DRAM refresh rate  Device 0 Offset 6a
 564
 565     Units of 16 DRAM clock cycles.  (See 4.4.1 pg 39)
 566
 567     Rx69 (DRAM freq)  Rx58 (chip tech)  Rx6a
 568
 569     133Mhz            64/128Mb          0x86
 570     133Mhz            256/512Mb         0x43
 571     100Mhz            64/128Mb          0x65
 572     100Mhz            256/512Mb         0x32
 573 */
 574
 575         b = pci_read_config8(north,0x58);
 576         if( b < 0x80 )   // 256 tech
 577                 pci_write_config8(north,0x6a,0x86);
 578         else
 579                 pci_write_config8(north,0x6a,0x43);
 580
 581         pci_write_config8(north,0x61,0xff);
 582         //pci_write_config8(north,0x67,0x22);
 583
 584         /* pci */
 585         pci_write_config8(north,0x70,0x82);
 586         pci_write_config8(north,0x73,0x01);
 587         pci_write_config8(north,0x76,0x50);
 588
 589
 590         pci_write_config8(north,0x71,0xc8);
 591
 592
 593         /* graphics aperture base */
 594
 595         pci_write_config8(north,0x13,0xd0);
 596
 597         //pci_write_config8(north,0xe1,0xdf);
 598         //pci_write_config8(north,0xe2,0x42);
 599         pci_write_config8(north,0xe0,0x00);
 600
 601         pci_write_config8(north,0x84,0x80);
 602         pci_write_config16(north,0x80,0x610f);
 603         pci_write_config32(north,0x88,0x00000002);
 604
 605
 606
 607         pci_write_config8(north,0xa8,0x04);
 608         pci_write_config8(north,0xac,0x2f);
 609         pci_write_config8(north,0xae,0x04);
 610
 611         print_debug("vt8623 done\n");
 612         dumpnorth(north);
 613
 614         print_debug("AGP\n");
 615         north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
 616         pci_write_config32(north,0x20,0xddf0dc00);
 617         pci_write_config32(north,0x24,0xdbf0d800);
 618         pci_write_config8(north,0x3e,0x0c);
 619         //dumpnorth(north);
 620
 621         //print_err("VGA\n");
 622         //north = pci_locate_device(PCI_ID(0x1106, 0x3122), 0);
 623         //pci_write_config32(north,0x10,0xd8000008);
 624         //pci_write_config32(north,0x14,0xdc000000);
 625         //dumpnorth(north);
 626
 627 }