1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/hypertransport.h>
7 #include <device/pci_ids.h>
12 #include <cpu/x86/mtrr.h>
13 #include <cpu/x86/msr.h>
15 #include "northbridge.h"
18 * This fixup is based on capturing values from an Award BIOS. Without
19 * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
20 * slower than normal, ethernet drops packets).
21 * Apparently these registers govern some sort of bus master behavior.
24 static void northbridge_init(device_t dev)
30 printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
31 pci_write_config8(dev, 0x0d, 0x08);
32 pci_write_config8(dev, 0x70, 0x82);
33 pci_write_config8(dev, 0x71, 0xc8);
34 pci_write_config8(dev, 0x72, 0x00);
35 pci_write_config8(dev, 0x73, 0x01);
36 pci_write_config8(dev, 0x74, 0x01);
37 pci_write_config8(dev, 0x75, 0x08);
38 pci_write_config8(dev, 0x76, 0x52);
39 pci_write_config8(dev, 0x13, 0xd0);
40 pci_write_config8(dev, 0x84, 0x80);
41 pci_write_config16(dev, 0x80, 0x610f);
42 pci_write_config32(dev, 0x88, 0x00000002);
44 fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
46 /* Fixup GART and framebuffer addresses properly.
47 * First setup frame buffer properly.
49 //fb = pci_read_config32(dev, 0x10); /* Base addres of framebuffer */
51 printk(BIOS_DEBUG, "Frame buffer at %8x\n",fb);
53 c = pci_read_config8(dev, 0xe1) & 0xf0; /* size of vga */
54 c |= fb>>28; /* upper nibble of frame buffer address */
56 pci_write_config8(dev, 0xe1, c);
57 c = 0x81; /* enable framebuffer */
58 pci_write_config8(dev, 0xe0, c);
59 pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */
63 static void nullfunc(){}
65 static struct device_operations northbridge_operations = {
66 .read_resources = nullfunc,
67 .set_resources = pci_dev_set_resources,
68 .enable_resources = pci_dev_enable_resources,
69 .init = northbridge_init
72 static const struct pci_driver northbridge_driver __pci_driver = {
73 .ops = &northbridge_operations,
74 .vendor = PCI_VENDOR_ID_VIA,
75 .device = PCI_DEVICE_ID_VIA_8623,
78 static void agp_init(device_t dev)
80 printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
82 pci_write_config8(dev, 0x3e, 0x0c);
83 pci_write_config8(dev, 0x40, 0x83);
84 pci_write_config8(dev, 0x41, 0xc5);
85 pci_write_config8(dev, 0x43, 0x44);
86 pci_write_config8(dev, 0x44, 0x34);
87 pci_write_config8(dev, 0x83, 0x02);
90 static struct device_operations agp_operations = {
91 .read_resources = nullfunc,
92 .set_resources = pci_dev_set_resources,
93 .enable_resources = pci_bus_enable_resources,
95 .scan_bus = pci_scan_bridge,
99 static const struct pci_driver agp_driver __pci_driver = {
100 .ops = &agp_operations,
101 .vendor = PCI_VENDOR_ID_VIA,
102 .device = PCI_DEVICE_ID_VIA_8633_1,
105 static void vga_init(device_t dev)
108 msr_t clocks1,clocks2,instructions,setup;
110 printk(BIOS_DEBUG, "VGA random fixup ...\n");
111 pci_write_config8(dev, 0x04, 0x07);
112 pci_write_config8(dev, 0x0d, 0x20);
113 pci_write_config32(dev,0x10,0xd8000008);
114 pci_write_config32(dev,0x14,0xdc000000);
116 // set up performnce counters for debugging vga init sequence
117 //setup.lo = 0x1c0; // count instructions
118 //wrmsr(0x187,setup);
119 //instructions.hi = 0;
120 //instructions.lo = 0;
121 //wrmsr(0xc2,instructions);
122 //clocks1 = rdmsr(0x10);
126 /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
129 call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
131 //clocks2 = rdmsr(0x10);
132 //instructions = rdmsr(0xc2);
134 printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
135 printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
136 printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
140 /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
141 printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
142 setup_realmode_idt();
143 printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
146 //clocks2 = rdmsr(0x10);
147 //instructions = rdmsr(0xc2);
149 //printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
150 //printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
151 //printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
153 vga_enable_console();
157 pci_write_config32(dev,0x30,0);
159 /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
161 add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
162 fb = pci_read_config32(dev,0x10); // get the fb address
163 add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
167 static struct device_operations vga_operations = {
168 .read_resources = pci_dev_read_resources,
169 .set_resources = pci_dev_set_resources,
170 .enable_resources = pci_dev_enable_resources,
175 static const struct pci_driver vga_driver __pci_driver = {
176 .ops = &vga_operations,
177 .vendor = PCI_VENDOR_ID_VIA,
181 static void ram_resource(device_t dev, unsigned long index,
182 unsigned long basek, unsigned long sizek)
184 struct resource *resource;
189 resource = new_resource(dev, index);
190 resource->base = ((resource_t)basek) << 10;
191 resource->size = ((resource_t)sizek) << 10;
192 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
193 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
196 static void tolm_test(void *gp, struct device *dev, struct resource *new)
198 struct resource **best_p = gp;
199 struct resource *best;
201 if (!best || (best->base > new->base)) {
207 static uint32_t find_pci_tolm(struct bus *bus)
209 struct resource *min;
212 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
214 if (min && tolm > min->base) {
220 #if CONFIG_WRITE_HIGH_TABLES==1
221 /* maximum size of high tables in KB */
222 #define HIGH_TABLES_SIZE 64
223 extern uint64_t high_tables_base, high_tables_size;
226 static void pci_domain_set_resources(device_t dev)
228 static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
232 printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
234 pci_tolm = find_pci_tolm(&dev->link[0]);
235 mc_dev = dev->link[0].children;
237 unsigned long tomk, tolmk;
238 unsigned char rambits;
241 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
243 reg = pci_read_config8(mc_dev, ramregs[i]);
244 /* these are ENDING addresses, not sizes.
245 * if there is memory in this slot, then reg will be > rambits.
246 * So we just take the max, that gives us total.
247 * We take the highest one to cover for once and future coreboot
248 * bugs. We warn about bugs.
253 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
256 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
257 tomk = rambits*16*1024 - 32768;
258 /* Compute the top of Low memory */
259 tolmk = pci_tolm >> 10;
261 /* The PCI hole does does not overlap the memory.
266 #if CONFIG_WRITE_HIGH_TABLES == 1
267 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
268 high_tables_size = HIGH_TABLES_SIZE* 1024;
269 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
272 /* Report the memory regions */
274 ram_resource(dev, idx++, 0, 640); /* first 640k */
275 ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
277 assign_resources(&dev->link[0]);
280 static struct device_operations pci_domain_ops = {
281 .read_resources = pci_domain_read_resources,
282 .set_resources = pci_domain_set_resources,
283 .enable_resources = enable_childrens_resources,
285 .scan_bus = pci_domain_scan_bus,
288 static void cpu_bus_init(device_t dev)
290 initialize_cpus(&dev->link[0]);
293 static void cpu_bus_noop(device_t dev)
297 static struct device_operations cpu_bus_ops = {
298 .read_resources = cpu_bus_noop,
299 .set_resources = cpu_bus_noop,
300 .enable_resources = cpu_bus_noop,
301 .init = cpu_bus_init,
305 static void enable_dev(struct device *dev)
307 printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
309 /* Set the operations if it is a special bus type */
310 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
311 dev->ops = &pci_domain_ops;
314 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
315 dev->ops = &cpu_bus_ops;
319 struct chip_operations northbridge_via_vt8623_ops = {
320 CHIP_NAME("VIA VT8623 Northbridge")
321 .enable_dev = enable_dev,