1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/hypertransport.h>
7 #include <device/pci_ids.h>
12 #include <cpu/x86/mtrr.h>
13 #include <cpu/x86/msr.h>
15 #include "northbridge.h"
18 * This fixup is based on capturing values from an Award BIOS. Without
19 * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
20 * slower than normal, ethernet drops packets).
21 * Apparently these registers govern some sort of bus master behavior.
24 static void northbridge_init(device_t dev)
30 printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
31 pci_write_config8(dev, 0x0d, 0x08);
32 pci_write_config8(dev, 0x70, 0x82);
33 pci_write_config8(dev, 0x71, 0xc8);
34 pci_write_config8(dev, 0x72, 0x00);
35 pci_write_config8(dev, 0x73, 0x01);
36 pci_write_config8(dev, 0x74, 0x01);
37 pci_write_config8(dev, 0x75, 0x08);
38 pci_write_config8(dev, 0x76, 0x52);
39 pci_write_config8(dev, 0x13, 0xd0);
40 pci_write_config8(dev, 0x84, 0x80);
41 pci_write_config16(dev, 0x80, 0x610f);
42 pci_write_config32(dev, 0x88, 0x00000002);
44 fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
46 /* Fixup GART and framebuffer addresses properly.
47 * First setup frame buffer properly.
49 //fb = pci_read_config32(dev, 0x10); /* Base addres of framebuffer */
51 printk(BIOS_DEBUG, "Frame buffer at %8lx\n",fb);
53 c = pci_read_config8(dev, 0xe1) & 0xf0; /* size of vga */
54 c |= fb>>28; /* upper nibble of frame buffer address */
56 pci_write_config8(dev, 0xe1, c);
57 c = 0x81; /* enable framebuffer */
58 pci_write_config8(dev, 0xe0, c);
59 pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */
63 static void nullfunc(device_t dev)
68 static struct device_operations northbridge_operations = {
69 .read_resources = nullfunc,
70 .set_resources = pci_dev_set_resources,
71 .enable_resources = pci_dev_enable_resources,
72 .init = northbridge_init
75 static const struct pci_driver northbridge_driver __pci_driver = {
76 .ops = &northbridge_operations,
77 .vendor = PCI_VENDOR_ID_VIA,
78 .device = PCI_DEVICE_ID_VIA_8623,
81 static void agp_init(device_t dev)
83 printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
85 pci_write_config8(dev, 0x3e, 0x0c);
86 pci_write_config8(dev, 0x40, 0x83);
87 pci_write_config8(dev, 0x41, 0xc5);
88 pci_write_config8(dev, 0x43, 0x44);
89 pci_write_config8(dev, 0x44, 0x34);
90 pci_write_config8(dev, 0x83, 0x02);
93 static struct device_operations agp_operations = {
94 .read_resources = nullfunc,
95 .set_resources = pci_dev_set_resources,
96 .enable_resources = pci_bus_enable_resources,
98 .scan_bus = pci_scan_bridge,
102 static const struct pci_driver agp_driver __pci_driver = {
103 .ops = &agp_operations,
104 .vendor = PCI_VENDOR_ID_VIA,
105 .device = PCI_DEVICE_ID_VIA_8633_1,
108 static void ram_resource(device_t dev, unsigned long index,
109 unsigned long basek, unsigned long sizek)
111 struct resource *resource;
116 resource = new_resource(dev, index);
117 resource->base = ((resource_t)basek) << 10;
118 resource->size = ((resource_t)sizek) << 10;
119 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
120 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
123 static void tolm_test(void *gp, struct device *dev, struct resource *new)
125 struct resource **best_p = gp;
126 struct resource *best;
128 if (!best || (best->base > new->base)) {
134 static uint32_t find_pci_tolm(struct bus *bus)
136 struct resource *min;
139 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
141 if (min && tolm > min->base) {
147 #if CONFIG_WRITE_HIGH_TABLES==1
148 /* maximum size of high tables in KB */
149 #define HIGH_TABLES_SIZE 64
150 extern uint64_t high_tables_base, high_tables_size;
153 static void pci_domain_set_resources(device_t dev)
155 static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
159 printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
161 pci_tolm = find_pci_tolm(&dev->link[0]);
162 mc_dev = dev->link[0].children;
164 unsigned long tomk, tolmk;
165 unsigned char rambits;
168 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
170 reg = pci_read_config8(mc_dev, ramregs[i]);
171 /* these are ENDING addresses, not sizes.
172 * if there is memory in this slot, then reg will be > rambits.
173 * So we just take the max, that gives us total.
174 * We take the highest one to cover for once and future coreboot
175 * bugs. We warn about bugs.
180 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
183 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
184 tomk = rambits*16*1024 - 32768;
185 /* Compute the top of Low memory */
186 tolmk = pci_tolm >> 10;
188 /* The PCI hole does does not overlap the memory.
193 #if CONFIG_WRITE_HIGH_TABLES == 1
194 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
195 high_tables_size = HIGH_TABLES_SIZE* 1024;
196 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
199 /* Report the memory regions */
201 ram_resource(dev, idx++, 0, 640); /* first 640k */
202 ram_resource(dev, idx++, 768, tolmk - 768); /* leave a hole for vga */
204 assign_resources(&dev->link[0]);
207 static struct device_operations pci_domain_ops = {
208 .read_resources = pci_domain_read_resources,
209 .set_resources = pci_domain_set_resources,
210 .enable_resources = enable_childrens_resources,
212 .scan_bus = pci_domain_scan_bus,
215 static void cpu_bus_init(device_t dev)
217 initialize_cpus(&dev->link[0]);
220 static void cpu_bus_noop(device_t dev)
224 static struct device_operations cpu_bus_ops = {
225 .read_resources = cpu_bus_noop,
226 .set_resources = cpu_bus_noop,
227 .enable_resources = cpu_bus_noop,
228 .init = cpu_bus_init,
232 static void enable_dev(struct device *dev)
234 printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
236 /* Set the operations if it is a special bus type */
237 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
238 dev->ops = &pci_domain_ops;
241 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
242 dev->ops = &cpu_bus_ops;
246 struct chip_operations northbridge_via_vt8623_ops = {
247 CHIP_NAME("VIA VT8623 Northbridge")
248 .enable_dev = enable_dev,