src/northbridge/via/vt8623/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <device/pci_ids.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include <cpu/x86/mtrr.h>
  13 #include <cpu/x86/msr.h>
  14 #include "chip.h"
  15 #include "northbridge.h"
  16
  17 /*
  18  * This fixup is based on capturing values from an Award BIOS.  Without
  19  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  20  * slower than normal, ethernet drops packets).
  21  * Apparently these registers govern some sort of bus master behavior.
  22  */
  23
  24 static void northbridge_init(device_t dev)
  25 {
  26         device_t fb_dev;
  27         unsigned long fb;
  28         unsigned char c;
  29
  30         printk_debug("VT8623 random fixup ...\n");
  31         pci_write_config8(dev,  0x0d, 0x08);
  32         pci_write_config8(dev,  0x70, 0x82);
  33         pci_write_config8(dev,  0x71, 0xc8);
  34         pci_write_config8(dev,  0x72, 0x00);
  35         pci_write_config8(dev,  0x73, 0x01);
  36         pci_write_config8(dev,  0x74, 0x01);
  37         pci_write_config8(dev,  0x75, 0x08);
  38         pci_write_config8(dev,  0x76, 0x52);
  39         pci_write_config8(dev,  0x13, 0xd0);
  40         pci_write_config8(dev,  0x84, 0x80);
  41         pci_write_config16(dev, 0x80, 0x610f);
  42         pci_write_config32(dev, 0x88, 0x00000002);
  43
  44         fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  45         if (fb_dev) {
  46                 /* Fixup GART and framebuffer addresses properly.
  47                  * First setup frame buffer properly.
  48                  */
  49                 //fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
  50                 fb = 0xd0000000;
  51                 printk_debug("Frame buffer at %8x\n",fb);
  52
  53                 c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
  54                 c |= fb>>28;  /* upper nibble of frame buffer address */
  55                 c = 0xdd;
  56                 pci_write_config8(dev, 0xe1, c);
  57                 c = 0x81;                                /* enable framebuffer */
  58                 pci_write_config8(dev, 0xe0, c);
  59                 pci_write_config8(dev, 0xe2, 0x42);      /* 'cos award does */
  60         }
  61 }
  62
  63 static void nullfunc(){}
  64
  65 static struct device_operations northbridge_operations = {
  66         .read_resources   = nullfunc,
  67         .set_resources    = pci_dev_set_resources,
  68         .enable_resources = pci_dev_enable_resources,
  69         .init             = northbridge_init
  70 };
  71
  72 static const struct pci_driver northbridge_driver __pci_driver = {
  73         .ops = &northbridge_operations,
  74         .vendor = PCI_VENDOR_ID_VIA,
  75         .device = PCI_DEVICE_ID_VIA_8623,
  76 };
  77
  78 static void agp_init(device_t dev)
  79 {
  80         printk_debug("VT8623 AGP random fixup ...\n");
  81
  82         pci_write_config8(dev, 0x3e, 0x0c);
  83         pci_write_config8(dev, 0x40, 0x83);
  84         pci_write_config8(dev, 0x41, 0xc5);
  85         pci_write_config8(dev, 0x43, 0x44);
  86         pci_write_config8(dev, 0x44, 0x34);
  87         pci_write_config8(dev, 0x83, 0x02);
  88 }
  89
  90 static struct device_operations agp_operations = {
  91         .read_resources   = nullfunc,
  92         .set_resources    = pci_dev_set_resources,
  93         .enable_resources = pci_bus_enable_resources,
  94         .init             = agp_init,
  95         .scan_bus         = pci_scan_bridge,
  96         .ops_pci          = 0,
  97 };
  98
  99 static const struct pci_driver agp_driver __pci_driver = {
 100         .ops = &agp_operations,
 101         .vendor = PCI_VENDOR_ID_VIA,
 102         .device = PCI_DEVICE_ID_VIA_8633_1,
 103 };
 104
 105 static void vga_init(device_t dev)
 106 {
 107 //      unsigned long fb;
 108         msr_t clocks1,clocks2,instructions,setup;
 109
 110         printk_debug("VGA random fixup ...\n");
 111         pci_write_config8(dev, 0x04, 0x07);
 112         pci_write_config8(dev, 0x0d, 0x20);
 113         pci_write_config32(dev,0x10,0xd8000008);
 114         pci_write_config32(dev,0x14,0xdc000000);
 115
 116         // set up performnce counters for debugging vga init sequence
 117         //setup.lo = 0x1c0; // count instructions
 118         //wrmsr(0x187,setup);
 119         //instructions.hi = 0;
 120         //instructions.lo = 0;
 121         //wrmsr(0xc2,instructions);
 122         //clocks1 = rdmsr(0x10);
 123
 124
 125 #if 0
 126         /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
 127         dev->on_mainboard=1;
 128         dev->rom_address = (void *)0xfffc0000;
 129
 130         pci_dev_init(dev);
 131
 132         call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 133
 134         //clocks2 = rdmsr(0x10);
 135         //instructions = rdmsr(0xc2);
 136
 137         printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 138         printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 139         printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 140
 141 #else
 142
 143         /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
 144         printk_debug("INSTALL REAL-MODE IDT\n");
 145         setup_realmode_idt();
 146         printk_debug("DO THE VGA BIOS\n");
 147         do_vgabios();
 148
 149         //clocks2 = rdmsr(0x10);
 150         //instructions = rdmsr(0xc2);
 151
 152         //printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 153         //printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 154         //printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 155
 156         vga_enable_console();
 157
 158 #endif
 159
 160         pci_write_config32(dev,0x30,0);
 161
 162         /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
 163 #if 0
 164         add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
 165         fb = pci_read_config32(dev,0x10); // get the fb address
 166         add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
 167 #endif
 168 }
 169
 170 static void vga_read_resources(device_t dev)
 171 {
 172
 173         dev->rom_address = (void *)0xfffc0000;
 174         dev->on_mainboard=1;
 175         pci_dev_read_resources(dev);
 176
 177 }
 178
 179 static struct device_operations vga_operations = {
 180         .read_resources   = vga_read_resources,
 181         .set_resources    = pci_dev_set_resources,
 182         .enable_resources = pci_dev_enable_resources,
 183         .init             = vga_init,
 184         .ops_pci          = 0,
 185 };
 186
 187 static const struct pci_driver vga_driver __pci_driver = {
 188         .ops = &vga_operations,
 189         .vendor = PCI_VENDOR_ID_VIA,
 190         .device = 0x3122,
 191 };
 192
 193
 194 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 195
 196 static void pci_domain_read_resources(device_t dev)
 197 {
 198         struct resource *resource;
 199
 200         printk_spew("Entering vt8623 pci_domain_read_resources.\n");
 201
 202         /* Initialize the system wide io space constraints */
 203         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
 204         resource->limit = 0xffffUL;
 205         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 206                 IORESOURCE_ASSIGNED;
 207
 208         /* Initialize the system wide memory resources constraints */
 209         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
 210         resource->limit = 0xffffffffULL;
 211         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 212                 IORESOURCE_ASSIGNED;
 213
 214         printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
 215 }
 216
 217 static void ram_resource(device_t dev, unsigned long index,
 218         unsigned long basek, unsigned long sizek)
 219 {
 220         struct resource *resource;
 221
 222         if (!sizek) {
 223                 return;
 224         }
 225         resource = new_resource(dev, index);
 226         resource->base  = ((resource_t)basek) << 10;
 227         resource->size  = ((resource_t)sizek) << 10;
 228         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 229                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 230 }
 231
 232 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 233 {
 234         struct resource **best_p = gp;
 235         struct resource *best;
 236         best = *best_p;
 237         if (!best || (best->base > new->base)) {
 238                 best = new;
 239         }
 240         *best_p = best;
 241 }
 242
 243 static uint32_t find_pci_tolm(struct bus *bus)
 244 {
 245         struct resource *min;
 246         uint32_t tolm;
 247         min = 0;
 248         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 249         tolm = 0xffffffffUL;
 250         if (min && tolm > min->base) {
 251                 tolm = min->base;
 252         }
 253         return tolm;
 254 }
 255
 256 #if CONFIG_HAVE_HIGH_TABLES==1
 257 /* maximum size of high tables in KB */
 258 #define HIGH_TABLES_SIZE 64
 259 extern uint64_t high_tables_base, high_tables_size;
 260 #endif
 261
 262 static void pci_domain_set_resources(device_t dev)
 263 {
 264         static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
 265         device_t mc_dev;
 266         uint32_t pci_tolm;
 267
 268         printk_spew("Entering vt8623 pci_domain_set_resources.\n");
 269
 270         pci_tolm = find_pci_tolm(&dev->link[0]);
 271         mc_dev = dev->link[0].children;
 272         if (mc_dev) {
 273                 unsigned long tomk, tolmk;
 274                 unsigned char rambits;
 275                 int i, idx;
 276
 277                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 278                         unsigned char reg;
 279                         reg = pci_read_config8(mc_dev, ramregs[i]);
 280                         /* these are ENDING addresses, not sizes.
 281                          * if there is memory in this slot, then reg will be > rambits.
 282                          * So we just take the max, that gives us total.
 283                          * We take the highest one to cover for once and future coreboot
 284                          * bugs. We warn about bugs.
 285                          */
 286                         if (reg > rambits)
 287                                 rambits = reg;
 288                         if (reg < rambits)
 289                                 printk_err("ERROR! register 0x%x is not set!\n",
 290                                         ramregs[i]);
 291                 }
 292                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 293                 tomk = rambits*16*1024 - 32768;
 294                 /* Compute the top of Low memory */
 295                 tolmk = pci_tolm >> 10;
 296                 if (tolmk >= tomk) {
 297                         /* The PCI hole does does not overlap the memory.
 298                          */
 299                         tolmk = tomk;
 300                 }
 301
 302 #if CONFIG_HAVE_HIGH_TABLES == 1
 303                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 304                 high_tables_size = HIGH_TABLES_SIZE* 1024;
 305                 printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 306 #endif
 307
 308                 /* Report the memory regions */
 309                 idx = 10;
 310                 ram_resource(dev, idx++, 0, 640);               /* first 640k */
 311                 ram_resource(dev, idx++, 768, tolmk - 768);     /* leave a hole for vga */
 312         }
 313         assign_resources(&dev->link[0]);
 314 }
 315
 316 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 317 {
 318         printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
 319
 320         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 321         return max;
 322 }
 323
 324 static struct device_operations pci_domain_ops = {
 325         .read_resources   = pci_domain_read_resources,
 326         .set_resources    = pci_domain_set_resources,
 327         .enable_resources = enable_childrens_resources,
 328         .init             = 0,
 329         .scan_bus         = pci_domain_scan_bus,
 330 };
 331
 332 static void cpu_bus_init(device_t dev)
 333 {
 334         initialize_cpus(&dev->link[0]);
 335 }
 336
 337 static void cpu_bus_noop(device_t dev)
 338 {
 339 }
 340
 341 static struct device_operations cpu_bus_ops = {
 342         .read_resources   = cpu_bus_noop,
 343         .set_resources    = cpu_bus_noop,
 344         .enable_resources = cpu_bus_noop,
 345         .init             = cpu_bus_init,
 346         .scan_bus         = 0,
 347 };
 348
 349 static void enable_dev(struct device *dev)
 350 {
 351         printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
 352
 353         /* Set the operations if it is a special bus type */
 354         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 355                 dev->ops = &pci_domain_ops;
 356                 pci_set_method(dev);
 357         }
 358         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 359                 dev->ops = &cpu_bus_ops;
 360         }
 361 }
 362
 363 struct chip_operations northbridge_via_vt8623_ops = {
 364         CHIP_NAME("VIA VT8623 Northbridge")
 365         .enable_dev = enable_dev,
 366 };