src/northbridge/via/vt8601/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <cpu/cpu.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <bitops.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14
  15 /*
  16  * This fixup is based on capturing values from an Award bios.  Without
  17  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  18  * slower than normal, ethernet drops packets).
  19  * Apparently these registers govern some sort of bus master behavior.
  20  */
  21 static void northbridge_init(device_t dev)
  22 {
  23         printk_spew("VT8601 random fixup ...\n");
  24         pci_write_config8(dev, 0x70, 0xc0);
  25         pci_write_config8(dev, 0x71, 0x88);
  26         pci_write_config8(dev, 0x72, 0xec);
  27         pci_write_config8(dev, 0x73, 0x0c);
  28         pci_write_config8(dev, 0x74, 0x0e);
  29         pci_write_config8(dev, 0x75, 0x81);
  30         pci_write_config8(dev, 0x76, 0x52);
  31 }
  32
  33 static struct device_operations northbridge_operations = {
  34         .read_resources   = pci_dev_read_resources,
  35         .set_resources    = pci_dev_set_resources,
  36         .enable_resources = pci_dev_enable_resources,
  37         .init             = northbridge_init,
  38         .enable           = 0,
  39         .ops_pci          = 0,
  40 };
  41
  42 static const struct pci_driver northbridge_driver __pci_driver = {
  43         .ops = &northbridge_operations,
  44         .vendor = PCI_VENDOR_ID_VIA,
  45         .device = 0x0601, /* 0x8601 is the AGP bridge? */
  46 };
  47
  48 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  49
  50 static void pci_domain_read_resources(device_t dev)
  51 {
  52         struct resource *resource;
  53
  54         /* Initialize the system wide io space constraints */
  55         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  56         resource->limit = 0xffffUL;
  57         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  58
  59         /* Initialize the system wide memory resources constraints */
  60         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  61         resource->limit = 0xffffffffULL;
  62         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  63 }
  64
  65 static void ram_resource(device_t dev, unsigned long index,
  66         unsigned long basek, unsigned long sizek)
  67 {
  68         struct resource *resource;
  69
  70         if (!sizek) {
  71                 return;
  72         }
  73         resource = new_resource(dev, index);
  74         resource->base  = ((resource_t)basek) << 10;
  75         resource->size  = ((resource_t)sizek) << 10;
  76         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  77                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  78 }
  79
  80 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  81 {
  82         struct resource **best_p = gp;
  83         struct resource *best;
  84         best = *best_p;
  85         if (!best || (best->base > new->base)) {
  86                 best = new;
  87         }
  88         *best_p = best;
  89 }
  90
  91 static uint32_t find_pci_tolm(struct bus *bus)
  92 {
  93         struct resource *min;
  94         uint32_t tolm;
  95         min = 0;
  96         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  97         tolm = 0xffffffffUL;
  98         if (min && tolm > min->base) {
  99                 tolm = min->base;
 100         }
 101         return tolm;
 102 }
 103
 104 #if HAVE_HIGH_TABLES==1
 105 /* maximum size of high tables in KB */
 106 #define HIGH_TABLES_SIZE 64
 107 extern uint64_t high_tables_base, high_tables_size;
 108 #endif
 109
 110 static void pci_domain_set_resources(device_t dev)
 111 {
 112         static const uint8_t ramregs[] = {
 113                 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 114         };
 115         device_t mc_dev;
 116         uint32_t pci_tolm;
 117
 118         pci_tolm = find_pci_tolm(&dev->link[0]);
 119         mc_dev = dev->link[0].children;
 120         if (mc_dev) {
 121                 unsigned long tomk, tolmk;
 122                 unsigned char rambits;
 123                 int i, idx;
 124
 125                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 126                         unsigned char reg;
 127                         reg = pci_read_config8(mc_dev, ramregs[i]);
 128                         /* these are ENDING addresses, not sizes.
 129                          * if there is memory in this slot, then reg will be > rambits.
 130                          * So we just take the max, that gives us total.
 131                          * We take the highest one to cover for once and future coreboot
 132                          * bugs. We warn about bugs.
 133                          */
 134                         if (reg > rambits)
 135                                 rambits = reg;
 136                         if (reg < rambits)
 137                                 printk_err("ERROR! register 0x%x is not set!\n",
 138                                         ramregs[i]);
 139                 }
 140                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 141                 tomk = rambits*8*1024;
 142                 /* Compute the top of Low memory */
 143                 tolmk = pci_tolm >> 10;
 144                 if (tolmk >= tomk) {
 145                         /* The PCI hole does does not overlap the memory.
 146                          */
 147                         tolmk = tomk;
 148                 }
 149
 150 #if HAVE_HIGH_TABLES == 1
 151                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 152                 high_tables_size = HIGH_TABLES_SIZE* 1024;
 153                 printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 154 #endif
 155
 156                 /* Report the memory regions */
 157                 idx = 10;
 158                 ram_resource(dev, idx++, 0, tolmk);
 159         }
 160         assign_resources(&dev->link[0]);
 161 }
 162
 163 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 164 {
 165         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 166         return max;
 167 }
 168
 169 static struct device_operations pci_domain_ops = {
 170         .read_resources   = pci_domain_read_resources,
 171         .set_resources    = pci_domain_set_resources,
 172         .enable_resources = enable_childrens_resources,
 173         .init             = 0,
 174         .scan_bus         = pci_domain_scan_bus,
 175 };
 176
 177 static void cpu_bus_init(device_t dev)
 178 {
 179         initialize_cpus(&dev->link[0]);
 180 }
 181
 182 static void cpu_bus_noop(device_t dev)
 183 {
 184 }
 185
 186 static struct device_operations cpu_bus_ops = {
 187         .read_resources   = cpu_bus_noop,
 188         .set_resources    = cpu_bus_noop,
 189         .enable_resources = cpu_bus_noop,
 190         .init             = cpu_bus_init,
 191         .scan_bus         = 0,
 192 };
 193
 194 static void enable_dev(struct device *dev)
 195 {
 196         /* Set the operations if it is a special bus type */
 197         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 198                 dev->ops = &pci_domain_ops;
 199                 pci_set_method(dev);
 200         }
 201         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 202                 dev->ops = &cpu_bus_ops;
 203         }
 204 }
 205
 206 struct chip_operations northbridge_via_vt8601_ops = {
 207         CHIP_NAME("VIA VT8601 Northbridge")
 208         .enable_dev = enable_dev,
 209 };