src/northbridge/via/vt8601/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <cpu/cpu.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <bitops.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14
  15 /*
  16  * This fixup is based on capturing values from an Award bios.  Without
  17  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  18  * slower than normal, ethernet drops packets).
  19  * Apparently these registers govern some sort of bus master behavior.
  20  */
  21 static void northbridge_init(device_t dev)
  22 {
  23         printk(BIOS_SPEW, "VT8601 random fixup ...\n");
  24         pci_write_config8(dev, 0x70, 0xc0);
  25         pci_write_config8(dev, 0x71, 0x88);
  26         pci_write_config8(dev, 0x72, 0xec);
  27         pci_write_config8(dev, 0x73, 0x0c);
  28         pci_write_config8(dev, 0x74, 0x0e);
  29         pci_write_config8(dev, 0x75, 0x81);
  30         pci_write_config8(dev, 0x76, 0x52);
  31 }
  32
  33 static struct device_operations northbridge_operations = {
  34         .read_resources   = pci_dev_read_resources,
  35         .set_resources    = pci_dev_set_resources,
  36         .enable_resources = pci_dev_enable_resources,
  37         .init             = northbridge_init,
  38         .enable           = 0,
  39         .ops_pci          = 0,
  40 };
  41
  42 static const struct pci_driver northbridge_driver __pci_driver = {
  43         .ops = &northbridge_operations,
  44         .vendor = PCI_VENDOR_ID_VIA,
  45         .device = 0x0601, /* 0x8601 is the AGP bridge? */
  46 };
  47
  48 static void ram_resource(device_t dev, unsigned long index,
  49         unsigned long basek, unsigned long sizek)
  50 {
  51         struct resource *resource;
  52
  53         if (!sizek) {
  54                 return;
  55         }
  56         resource = new_resource(dev, index);
  57         resource->base  = ((resource_t)basek) << 10;
  58         resource->size  = ((resource_t)sizek) << 10;
  59         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  60                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  61 }
  62
  63 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  64 {
  65         struct resource **best_p = gp;
  66         struct resource *best;
  67         best = *best_p;
  68         if (!best || (best->base > new->base)) {
  69                 best = new;
  70         }
  71         *best_p = best;
  72 }
  73
  74 static uint32_t find_pci_tolm(struct bus *bus)
  75 {
  76         struct resource *min;
  77         uint32_t tolm;
  78         min = 0;
  79         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  80         tolm = 0xffffffffUL;
  81         if (min && tolm > min->base) {
  82                 tolm = min->base;
  83         }
  84         return tolm;
  85 }
  86
  87 #if CONFIG_WRITE_HIGH_TABLES==1
  88 /* maximum size of high tables in KB */
  89 #define HIGH_TABLES_SIZE 64
  90 extern uint64_t high_tables_base, high_tables_size;
  91 #endif
  92
  93 static void pci_domain_set_resources(device_t dev)
  94 {
  95         static const uint8_t ramregs[] = {
  96                 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
  97         };
  98         device_t mc_dev;
  99         uint32_t pci_tolm;
 100
 101         pci_tolm = find_pci_tolm(dev->link_list);
 102         mc_dev = dev->link_list->children;
 103         if (mc_dev) {
 104                 unsigned long tomk, tolmk;
 105                 unsigned char rambits;
 106                 int i, idx;
 107
 108                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 109                         unsigned char reg;
 110                         reg = pci_read_config8(mc_dev, ramregs[i]);
 111                         /* these are ENDING addresses, not sizes.
 112                          * if there is memory in this slot, then reg will be > rambits.
 113                          * So we just take the max, that gives us total.
 114                          * We take the highest one to cover for once and future coreboot
 115                          * bugs. We warn about bugs.
 116                          */
 117                         if (reg > rambits)
 118                                 rambits = reg;
 119                         if (reg < rambits)
 120                                 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 121                                         ramregs[i]);
 122                 }
 123                 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 124                 tomk = rambits*8*1024;
 125                 /* Compute the top of Low memory */
 126                 tolmk = pci_tolm >> 10;
 127                 if (tolmk >= tomk) {
 128                         /* The PCI hole does does not overlap the memory.
 129                          */
 130                         tolmk = tomk;
 131                 }
 132
 133 #if CONFIG_WRITE_HIGH_TABLES == 1
 134                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 135                 high_tables_size = HIGH_TABLES_SIZE* 1024;
 136                 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 137 #endif
 138
 139                 /* Report the memory regions */
 140                 idx = 10;
 141                 ram_resource(dev, idx++, 0, tolmk);
 142         }
 143         assign_resources(dev->link_list);
 144 }
 145
 146 static struct device_operations pci_domain_ops = {
 147         .read_resources   = pci_domain_read_resources,
 148         .set_resources    = pci_domain_set_resources,
 149         .enable_resources = NULL,
 150         .init             = NULL,
 151         .scan_bus         = pci_domain_scan_bus,
 152 };
 153
 154 static void cpu_bus_init(device_t dev)
 155 {
 156         initialize_cpus(dev->link_list);
 157 }
 158
 159 static void cpu_bus_noop(device_t dev)
 160 {
 161 }
 162
 163 static struct device_operations cpu_bus_ops = {
 164         .read_resources   = cpu_bus_noop,
 165         .set_resources    = cpu_bus_noop,
 166         .enable_resources = cpu_bus_noop,
 167         .init             = cpu_bus_init,
 168         .scan_bus         = 0,
 169 };
 170
 171 static void enable_dev(struct device *dev)
 172 {
 173         /* Set the operations if it is a special bus type */
 174         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 175                 dev->ops = &pci_domain_ops;
 176                 pci_set_method(dev);
 177         }
 178         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 179                 dev->ops = &cpu_bus_ops;
 180         }
 181 }
 182
 183 struct chip_operations northbridge_via_vt8601_ops = {
 184         CHIP_NAME("VIA VT8601 Northbridge")
 185         .enable_dev = enable_dev,
 186 };