src/northbridge/via/vt8601/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include "chip.h"
  12 #include "northbridge.h"
  13
  14 /*
  15  * This fixup is based on capturing values from an Award bios.  Without
  16  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  17  * slower than normal, ethernet drops packets).
  18  * Apparently these registers govern some sort of bus master behavior.
  19  */
  20 static void northbridge_init(device_t dev)
  21 {
  22         printk_spew("VT8601 random fixup ...\n");
  23         pci_write_config8(dev, 0x70, 0xc0);
  24         pci_write_config8(dev, 0x71, 0x88);
  25         pci_write_config8(dev, 0x72, 0xec);
  26         pci_write_config8(dev, 0x73, 0x0c);
  27         pci_write_config8(dev, 0x74, 0x0e);
  28         pci_write_config8(dev, 0x75, 0x81);
  29         pci_write_config8(dev, 0x76, 0x52);
  30 }
  31
  32 static struct device_operations northbridge_operations = {
  33         .read_resources   = pci_dev_read_resources,
  34         .set_resources    = pci_dev_set_resources,
  35         .enable_resources = pci_dev_enable_resources,
  36         .init             = northbridge_init,
  37         .enable           = 0,
  38         .ops_pci          = 0,
  39 };
  40
  41 static const struct pci_driver northbridge_driver __pci_driver = {
  42         .ops = &northbridge_operations,
  43         .vendor = PCI_VENDOR_ID_VIA,
  44         .device = 0x0601, /* 0x8601 is the AGP bridge? */
  45 };
  46
  47 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  48
  49 static void pci_domain_read_resources(device_t dev)
  50 {
  51         struct resource *resource;
  52
  53         /* Initialize the system wide io space constraints */
  54         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  55         resource->limit = 0xffffUL;
  56         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  57
  58         /* Initialize the system wide memory resources constraints */
  59         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  60         resource->limit = 0xffffffffULL;
  61         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  62 }
  63
  64 static void ram_resource(device_t dev, unsigned long index,
  65         unsigned long basek, unsigned long sizek)
  66 {
  67         struct resource *resource;
  68
  69         if (!sizek) {
  70                 return;
  71         }
  72         resource = new_resource(dev, index);
  73         resource->base  = ((resource_t)basek) << 10;
  74         resource->size  = ((resource_t)sizek) << 10;
  75         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  76                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  77 }
  78
  79 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  80 {
  81         struct resource **best_p = gp;
  82         struct resource *best;
  83         best = *best_p;
  84         if (!best || (best->base > new->base)) {
  85                 best = new;
  86         }
  87         *best_p = best;
  88 }
  89
  90 static uint32_t find_pci_tolm(struct bus *bus)
  91 {
  92         struct resource *min;
  93         uint32_t tolm;
  94         min = 0;
  95         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  96         tolm = 0xffffffffUL;
  97         if (min && tolm > min->base) {
  98                 tolm = min->base;
  99         }
 100         return tolm;
 101 }
 102
 103 static void pci_domain_set_resources(device_t dev)
 104 {
 105         static const uint8_t ramregs[] = {
 106                 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 107         };
 108         device_t mc_dev;
 109         uint32_t pci_tolm;
 110
 111         pci_tolm = find_pci_tolm(&dev->link[0]);
 112         mc_dev = dev->link[0].children;
 113         if (mc_dev) {
 114                 unsigned long tomk, tolmk;
 115                 unsigned char rambits;
 116                 int i, idx;
 117
 118                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 119                         unsigned char reg;
 120                         reg = pci_read_config8(mc_dev, ramregs[i]);
 121                         /* these are ENDING addresses, not sizes.
 122                          * if there is memory in this slot, then reg will be > rambits.
 123                          * So we just take the max, that gives us total.
 124                          * We take the highest one to cover for once and future coreboot
 125                          * bugs. We warn about bugs.
 126                          */
 127                         if (reg > rambits)
 128                                 rambits = reg;
 129                         if (reg < rambits)
 130                                 printk_err("ERROR! register 0x%x is not set!\n",
 131                                         ramregs[i]);
 132                 }
 133                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 134                 tomk = rambits*8*1024;
 135                 /* Compute the top of Low memory */
 136                 tolmk = pci_tolm >> 10;
 137                 if (tolmk >= tomk) {
 138                         /* The PCI hole does does not overlap the memory.
 139                          */
 140                         tolmk = tomk;
 141                 }
 142                 /* Report the memory regions */
 143                 idx = 10;
 144                 ram_resource(dev, idx++, 0, tolmk);
 145         }
 146         assign_resources(&dev->link[0]);
 147 }
 148
 149 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 150 {
 151         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 152         return max;
 153 }
 154
 155 static struct device_operations pci_domain_ops = {
 156         .read_resources   = pci_domain_read_resources,
 157         .set_resources    = pci_domain_set_resources,
 158         .enable_resources = enable_childrens_resources,
 159         .init             = 0,
 160         .scan_bus         = pci_domain_scan_bus,
 161 };
 162
 163 static void cpu_bus_init(device_t dev)
 164 {
 165         initialize_cpus(&dev->link[0]);
 166 }
 167
 168 static void cpu_bus_noop(device_t dev)
 169 {
 170 }
 171
 172 static struct device_operations cpu_bus_ops = {
 173         .read_resources   = cpu_bus_noop,
 174         .set_resources    = cpu_bus_noop,
 175         .enable_resources = cpu_bus_noop,
 176         .init             = cpu_bus_init,
 177         .scan_bus         = 0,
 178 };
 179
 180 static void enable_dev(struct device *dev)
 181 {
 182         /* Set the operations if it is a special bus type */
 183         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 184                 dev->ops = &pci_domain_ops;
 185                 pci_set_method(dev);
 186         }
 187         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 188                 dev->ops = &cpu_bus_ops;
 189         }
 190 }
 191
 192 struct chip_operations northbridge_via_vt8601_ops = {
 193         CHIP_NAME("VIA VT8601 Northbridge")
 194         .enable_dev = enable_dev,
 195 };