2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/hypertransport.h>
26 #include <device/pci_ids.h>
31 #include <cpu/x86/mtrr.h>
33 #include "northbridge.h"
35 #if CONFIG_WRITE_HIGH_TABLES==1
36 /* maximum size of high tables in KB */
37 #define HIGH_TABLES_SIZE 64
38 extern uint64_t high_tables_base, high_tables_size;
41 static void pci_domain_set_resources(device_t dev)
46 unsigned long tomk, tolmk;
47 unsigned char rambits;
50 pci_tolm = find_pci_tolm(dev->link_list);
51 mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
53 rambits = pci_read_config8(mc_dev, 0x88);
56 /* Get memory size and frame buffer from northbridge's registers.
58 * If register contains an invalid value we set frame buffer size to a
59 * default of 32M, but that probably won't happen.
61 reg = pci_read_config8(mc_dev, 0xa1);
65 /* TOP 1M SMM Memory */
66 if (reg == 0x0 || reg == 0x6 || reg == 0x7)
67 tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default
69 tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
71 /* Compute the top of Low memory */
72 tolmk = pci_tolm >> 10;
74 /* The PCI hole does does not overlap the memory. */
76 tolmk -= 1024; // TOP 1M SM Memory
79 #if CONFIG_WRITE_HIGH_TABLES == 1
80 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
81 high_tables_size = HIGH_TABLES_SIZE* 1024;
82 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
85 /* Report the memory regions */
88 /* TODO: Hole needed? Should this go elsewhere? */
89 ram_resource(dev, idx++, 0, 640); /* first 640k */
90 ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */
91 assign_resources(dev->link_list);
94 static struct device_operations pci_domain_ops = {
95 .read_resources = pci_domain_read_resources,
96 .set_resources = pci_domain_set_resources,
97 .enable_resources = NULL,
99 .scan_bus = pci_domain_scan_bus,
102 static void cpu_bus_init(device_t dev)
104 initialize_cpus(dev->link_list);
107 static void cpu_bus_noop(device_t dev)
111 static struct device_operations cpu_bus_ops = {
112 .read_resources = cpu_bus_noop,
113 .set_resources = cpu_bus_noop,
114 .enable_resources = cpu_bus_noop,
115 .init = cpu_bus_init,
119 static void enable_dev(struct device *dev)
121 /* Our wonderful device model */
122 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
123 dev->ops = &pci_domain_ops;
125 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
126 dev->ops = &cpu_bus_ops;
130 struct chip_operations northbridge_via_cx700_ops = {
131 CHIP_NAME("VIA CX700 Northbridge")
132 .enable_dev = enable_dev