src/northbridge/via/cn700/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 VIA Technologies, Inc.
   5  * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
   6  * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 #include <spd.h>
  24 #include <delay.h>
  25 #include "cn700.h"
  26
  27 #ifdef CONFIG_DEBUG_RAM_SETUP
  28 #define PRINT_DEBUG_MEM(x)              print_debug(x)
  29 #define PRINT_DEBUG_MEM_HEX8(x)         print_debug_hex8(x)
  30 #define PRINT_DEBUG_MEM_HEX16(x)        print_debug_hex16(x)
  31 #define PRINT_DEBUG_MEM_HEX32(x)        print_debug_hex32(x)
  32 #define DUMPNORTH()                     dump_pci_device(PCI_DEV(0, 0, 0))
  33 #else
  34 #define PRINT_DEBUG_MEM(x)
  35 #define PRINT_DEBUG_MEM_HEX8(x)
  36 #define PRINT_DEBUG_MEM_HEX16(x)
  37 #define PRINT_DEBUG_MEM_HEX32(x)
  38 #define DUMPNORTH()
  39 #endif
  40
  41 static void do_ram_command(device_t dev, u8 command)
  42 {
  43         u8 reg;
  44
  45         /* TODO: Support for multiple DIMMs. */
  46
  47         reg = pci_read_config8(dev, DRAM_MISC_CTL);
  48         reg &= 0xf8;            /* Clear bits 2-0. */
  49         reg |= command;
  50         pci_write_config8(dev, DRAM_MISC_CTL, reg);
  51 }
  52
  53 /**
  54  * Configure the bus between the CPU and the northbridge. This might be able to
  55  * be moved to post-ram code in the future. For the most part, these registers
  56  * should not be messed around with. These are too complex to explain short of
  57  * copying the datasheets into the comments, but most of these values are from
  58  * the BIOS Porting Guide, so they should work on any board. If they don't,
  59  * try the values from your factory BIOS.
  60  *
  61  * TODO: Changing the DRAM frequency doesn't work (hard lockup).
  62  *
  63  * @param dev The northbridge's CPU Host Interface (D0F2).
  64  */
  65 static void c7_cpu_setup(device_t dev)
  66 {
  67         /* Host bus interface registers (D0F2 0x50-0x67) */
  68         /* Request phase control */
  69         pci_write_config8(dev, 0x50, 0x88);
  70         /* CPU Interface Control */
  71         pci_write_config8(dev, 0x51, 0x7a);
  72         pci_write_config8(dev, 0x52, 0x6f);
  73         /* Arbitration */
  74         pci_write_config8(dev, 0x53, 0x88);
  75         /* Miscellaneous Control */
  76         pci_write_config8(dev, 0x54, 0x1e);
  77         pci_write_config8(dev, 0x55, 0x16);
  78         /* Write Policy */
  79         pci_write_config8(dev, 0x56, 0x01);
  80         /* Miscellaneous Control */
  81         /*
  82          * DRAM Operating Frequency (bits 7:5)
  83          *      000 : 100MHz    001 : 133MHz
  84          *      010 : 166MHz    011 : 200MHz
  85          *      100 : 266MHz    101 : 333MHz
  86          *      110/111 : Reserved
  87          */
  88         /* CPU Miscellaneous Control */
  89         pci_write_config8(dev, 0x59, 0x44);
  90         /* Write Policy */
  91         pci_write_config8(dev, 0x5d, 0xb2);
  92         /* Bandwidth Timer */
  93         pci_write_config8(dev, 0x5e, 0x88);
  94         /* CPU Miscellaneous Control */
  95         pci_write_config8(dev, 0x5f, 0xc7);
  96
  97         /* Line DRDY# Timing Control */
  98         pci_write_config8(dev, 0x60, 0xff);
  99         pci_write_config8(dev, 0x61, 0xff);
 100         pci_write_config8(dev, 0x62, 0x0f);
 101         /* QW DRDY# Timing Control */
 102         pci_write_config8(dev, 0x63, 0xff);
 103         pci_write_config8(dev, 0x64, 0xff);
 104         pci_write_config8(dev, 0x65, 0x0f);
 105         /* Read Line Burst DRDY# Timing Control */
 106         pci_write_config8(dev, 0x66, 0xff);
 107         pci_write_config8(dev, 0x67, 0x30);
 108
 109         /* Host Bus I/O Circuit (see datasheet) */
 110         /* Host Address Pullup/down Driving */
 111         pci_write_config8(dev, 0x70, 0x11);
 112         pci_write_config8(dev, 0x71, 0x11);
 113         pci_write_config8(dev, 0x72, 0x11);
 114         pci_write_config8(dev, 0x73, 0x11);
 115         /* Miscellaneous Control */
 116         pci_write_config8(dev, 0x74, 0x35);
 117         /* AGTL+ I/O Circuit */
 118         pci_write_config8(dev, 0x75, 0x28);
 119         /* AGTL+ Compensation Status */
 120         pci_write_config8(dev, 0x76, 0x74);
 121         /* AGTL+ Auto Compensation Offest */
 122         pci_write_config8(dev, 0x77, 0x00);
 123         /* Host FSB CKG Control */
 124         pci_write_config8(dev, 0x78, 0x0a);
 125         /* Address/Address Clock Output Delay Control */
 126         pci_write_config8(dev, 0x79, 0xaa);
 127         /* Address Strobe Input Delay Control */
 128         pci_write_config8(dev, 0x7a, 0x24);
 129         /* Address CKG Rising/Falling Time Control */
 130         pci_write_config8(dev, 0x7b, 0xaa);
 131         /* Address CKG Clock Rising/Falling Time Control */
 132         pci_write_config8(dev, 0x7c, 0x00);
 133         /* Undefined (can't remember why I did this) */
 134         pci_write_config8(dev, 0x7d, 0x6d);
 135         pci_write_config8(dev, 0x7e, 0x00);
 136         pci_write_config8(dev, 0x7f, 0x00);
 137         pci_write_config8(dev, 0x80, 0x1b);
 138         pci_write_config8(dev, 0x81, 0x0a);
 139         pci_write_config8(dev, 0x82, 0x0a);
 140         pci_write_config8(dev, 0x83, 0x0a);
 141 }
 142
 143 /**
 144  * Set up DRAM size according to SPD data. Eventually, DRAM timings should be
 145  * done in a similar manner.
 146  *
 147  * @param ctrl The northbridge devices and SPD addresses.
 148  */
 149 static void sdram_set_size(const struct mem_controller *ctrl)
 150 {
 151         u8 density, ranks, result, col;
 152
 153         ranks = spd_read_byte(ctrl->channel0[0], SPD_NUM_DIMM_BANKS);
 154         ranks = (ranks & 0x07) + 1;
 155         density = spd_read_byte(ctrl->channel0[0],
 156                                 SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 157         switch (density) {
 158         case 0x80:
 159                 result = 0x08;  /* 512MB / 64MB = 0x08 */
 160                 break;
 161         case 0x40:
 162                 result = 0x04;
 163                 break;
 164         case 0x20:
 165                 result = 0x02;
 166                 break;
 167         case 0x10:
 168                 result = 0xff;  /* 16GB */
 169                 break;
 170         case 0x08:
 171                 result = 0xff;  /* 8GB */
 172                 break;
 173         case 0x04:
 174                 result = 0xff;  /* 4GB */
 175                 break;
 176         case 0x02:
 177                 result = 0x20;  /* 2GB */
 178                 break;
 179         case 0x01:
 180                 result = 0x10;  /* 1GB */
 181                 break;
 182         }
 183
 184         if (result == 0xff)
 185                 die("DRAM module size too big, not supported by CN700\n");
 186
 187         pci_write_config8(ctrl->d0f3, 0x40, result);
 188         pci_write_config8(ctrl->d0f3, 0x48, 0x00);
 189         if (ranks == 2) {
 190                 pci_write_config8(ctrl->d0f3, 0x41, result * ranks);
 191                 pci_write_config8(ctrl->d0f3, 0x49, result);
 192         }
 193         /* Size mirror */
 194         pci_write_config8(ctrl->d0f7, 0xe5, (result * ranks) << 2);
 195         pci_write_config8(ctrl->d0f7, 0x57, (result * ranks) << 2);
 196         /* Low Top Address */
 197         pci_write_config8(ctrl->d0f3, 0x84, 0x00);
 198         pci_write_config8(ctrl->d0f3, 0x85, (result * ranks) << 2);
 199         pci_write_config8(ctrl->d0f3, 0x88, (result * ranks) << 2);
 200
 201         /* Physical-Virtual Mapping */
 202         if (ranks == 2)
 203                 pci_write_config8(ctrl->d0f3, 0x54,
 204                                   1 << 7 | 0 << 4 | 1 << 3 | 1 << 0);
 205         if (ranks == 1)
 206                 pci_write_config8(ctrl->d0f3, 0x54, 1 << 7 | 0 << 4);
 207         pci_write_config8(ctrl->d0f3, 0x55, 0x00);
 208         /* Virtual rank interleave, disable */
 209         pci_write_config32(ctrl->d0f3, 0x58, 0x00);
 210
 211         /* MA Map Type */
 212         result = spd_read_byte(ctrl->channel0[0], SPD_NUM_BANKS_PER_SDRAM);
 213         if (result == 8) {
 214                 col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
 215                 switch (col) {
 216                 case 10:
 217                         pci_write_config8(ctrl->d0f3, 0x50, 0xa0);
 218                         break;
 219                 case 11:
 220                         pci_write_config8(ctrl->d0f3, 0x50, 0xc0);
 221                         break;
 222                 case 12:
 223                         pci_write_config8(ctrl->d0f3, 0x50, 0xe0);
 224                         break;
 225                 }
 226         } else if (result == 4) {
 227                 col = spd_read_byte(ctrl->channel0[0], SPD_NUM_COLUMNS);
 228                 switch (col) {
 229                 case 9:
 230                         pci_write_config8(ctrl->d0f3, 0x50, 0x00);
 231                         break;
 232                 case 10:
 233                         pci_write_config8(ctrl->d0f3, 0x50, 0x20);
 234                         break;
 235                 case 11:
 236                         pci_write_config8(ctrl->d0f3, 0x50, 0x40);
 237                         break;
 238                 case 12:
 239                         pci_write_config8(ctrl->d0f3, 0x50, 0x60);
 240                         break;
 241                 }
 242         }
 243         pci_write_config8(ctrl->d0f3, 0x51, 0x00);
 244 }
 245
 246 /**
 247  * Set up various RAM and other control registers statically. Some of these may
 248  * not be needed, other should be done with SPD info, but that's a project for
 249  * the future.
 250  */
 251 static void sdram_set_registers(const struct mem_controller *ctrl)
 252 {
 253         u8 reg;
 254
 255         /* Set WR=5 */
 256         pci_write_config8(ctrl->d0f3, 0x61, 0xe0);
 257         /* Set CAS=4 */
 258         pci_write_config8(ctrl->d0f3, 0x62, 0xfa);
 259         /* DRAM timing-3 */
 260         pci_write_config8(ctrl->d0f3, 0x63, 0xca);
 261         /* DRAM timing-4 */
 262         pci_write_config8(ctrl->d0f3, 0x64, 0xcc);
 263         /* DIMM command / Address Selection */
 264         pci_write_config8(ctrl->d0f3, 0x67, 0x00);
 265         /* Disable cross bank/multi page mode */
 266         pci_write_config8(ctrl->d0f3, 0x69, 0x00);
 267         /* Disable refresh now */
 268         pci_write_config8(ctrl->d0f3, 0x6a, 0x00);
 269
 270         /* Frequency 100 MHz */
 271         pci_write_config8(ctrl->d0f3, 0x90, 0x00);
 272         pci_write_config8(ctrl->d0f2, 0x57, 0x18);
 273         /* Allow manual DLL reset */
 274         pci_write_config8(ctrl->d0f3, 0x6b, 0x10);
 275
 276         /* Bank/Rank Interleave Address Select */
 277         pci_write_config8(ctrl->d0f3, 0x52, 0x33);
 278         pci_write_config8(ctrl->d0f3, 0x53, 0x3f);
 279
 280         /* Set to DDR2 SDRAM, BL=8 (0xc8, 0xc0 for bl=4) */
 281         pci_write_config8(ctrl->d0f3, 0x6c, 0xc8);
 282
 283         /* DRAM Bus Turn-Around Setting */
 284         pci_write_config8(ctrl->d0f3, 0x60, 0x03);
 285         /* DRAM Arbitration Control */
 286         pci_write_config8(ctrl->d0f3, 0x66, 0x80);
 287         /*
 288          * DQS Tuning: testing on a couple different boards has shown this is
 289          * static, or close enough that it can be. Which is good, because the
 290          * tuning function used too many registers.
 291          */
 292         /* DQS Output Delay for Channel A */
 293         pci_write_config8(ctrl->d0f3, 0x70, 0x00);
 294         /* MD Output Delay for Channel A */
 295         pci_write_config8(ctrl->d0f3, 0x71, 0x01);
 296         pci_write_config8(ctrl->d0f3, 0x73, 0x01);
 297
 298         /* DRAM arbitration timer */
 299         pci_write_config8(ctrl->d0f3, 0x65, 0xd9);
 300
 301         /* DRAM signal timing control */
 302         pci_write_config8(ctrl->d0f3, 0x74, 0x01);
 303         pci_write_config8(ctrl->d0f3, 0x75, 0x01);
 304         pci_write_config8(ctrl->d0f3, 0x76, 0x06);
 305         pci_write_config8(ctrl->d0f3, 0x77, 0x92);
 306         pci_write_config8(ctrl->d0f3, 0x78, 0x83);
 307         pci_write_config8(ctrl->d0f3, 0x79, 0x83);
 308         pci_write_config8(ctrl->d0f3, 0x7a, 0x00);
 309         pci_write_config8(ctrl->d0f3, 0x7b, 0x10);
 310
 311         /* DRAM clocking control */
 312         pci_write_config8(ctrl->d0f3, 0x91, 0x01);
 313         /* CS/CKE Clock Phase Control */
 314         pci_write_config8(ctrl->d0f3, 0x92, 0x02);
 315         /* SCMD/MA Clock Phase Control */
 316         pci_write_config8(ctrl->d0f3, 0x93, 0x02);
 317         /* DCLKO Feedback Mode Output Control */
 318         pci_write_config8(ctrl->d0f3, 0x94, 0x00);
 319         pci_write_config8(ctrl->d0f3, 0x9d, 0x0f);
 320
 321         /* SDRAM ODT Control */
 322         pci_write_config8(ctrl->d0f3, 0xda, 0x80);
 323         /* Channel A DQ/DQS CKG Output Delay Control */
 324         pci_write_config8(ctrl->d0f3, 0xdc, 0x54);
 325         /* Channel A DQ/DQS CKG Output Delay Control */
 326         pci_write_config8(ctrl->d0f3, 0xdd, 0x55);
 327         /* ODT lookup table */
 328         pci_write_config8(ctrl->d0f3, 0xd8, 0x01);
 329         pci_write_config8(ctrl->d0f3, 0xd9, 0x0a);
 330
 331         /* DDR SDRAM control */
 332         pci_write_config8(ctrl->d0f3, 0x6d, 0xc0);
 333         pci_write_config8(ctrl->d0f3, 0x6f, 0x41);
 334
 335         /* DQ/DQS Strength Control */
 336         pci_write_config8(ctrl->d0f3, 0xd0, 0xaa);
 337
 338         /* Compensation Control */
 339         pci_write_config8(ctrl->d0f3, 0xd3, 0x01); /* Enable autocompensation */
 340         /* ODT (some are set with driving select above) */
 341         pci_write_config8(ctrl->d0f3, 0xd4, 0x80);
 342         pci_write_config8(ctrl->d0f3, 0xd5, 0x8a);
 343         /* Memory Pads Driving and Range Select */
 344         pci_write_config8(ctrl->d0f3, 0xd6, 0xaa);
 345
 346         pci_write_config8(ctrl->d0f3, 0xe0, 0xee);
 347         pci_write_config8(ctrl->d0f3, 0xe2, 0xac);
 348         pci_write_config8(ctrl->d0f3, 0xe4, 0x66);
 349         pci_write_config8(ctrl->d0f3, 0xe6, 0x33);
 350         pci_write_config8(ctrl->d0f3, 0xe8, 0x86);
 351         /* DQS / DQ CKG Duty Cycle Control */
 352         pci_write_config8(ctrl->d0f3, 0xec, 0x00);
 353         /* MCLK Output Duty Control */
 354         pci_write_config8(ctrl->d0f3, 0xee, 0x00);
 355         /* DQS CKG Input Delay Control */
 356         pci_write_config8(ctrl->d0f3, 0xef, 0x10);
 357
 358         /* DRAM duty control */
 359         pci_write_config8(ctrl->d0f3, 0xed, 0x10);
 360
 361         /* SMM and APIC decoding, we do not use SMM */
 362         reg = 0x29;
 363         pci_write_config8(ctrl->d0f3, 0x86, reg);
 364         /* SMM and APIC decoding mirror */
 365         pci_write_config8(ctrl->d0f7, 0xe6, reg);
 366
 367         /* DRAM module configuration */
 368         pci_write_config8(ctrl->d0f3, 0x6e, 0x89);
 369 }
 370
 371 static void sdram_set_post(const struct mem_controller *ctrl)
 372 {
 373         device_t dev = ctrl->d0f3;
 374
 375         /* Enable multipage mode. */
 376         pci_write_config8(dev, 0x69, 0x03);
 377
 378         /* Enable refresh. */
 379         pci_write_config8(dev, 0x6a, 0x32);
 380
 381         /* VGA device. */
 382         pci_write_config16(dev, 0xa0, (1 << 15));
 383         pci_write_config16(dev, 0xa4, 0x0010);
 384 }
 385
 386 static void sdram_enable(device_t dev, unsigned long rank_address)
 387 {
 388         u8 i;
 389
 390         /* 1. Apply NOP. */
 391         PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
 392         do_ram_command(dev, RAM_COMMAND_NOP);
 393         udelay(100);
 394         read32(rank_address + 0x10);
 395
 396         /* 2. Precharge all. */
 397         udelay(400);
 398         PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
 399         do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 400         read32(rank_address + 0x10);
 401
 402         /* 3. Mode register set. */
 403         PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
 404         do_ram_command(dev, RAM_COMMAND_MRS);
 405         read32(rank_address + 0x120000);        /* EMRS DLL Enable */
 406         read32(rank_address + 0x800);           /* MRS DLL Reset */
 407
 408         /* 4. Precharge all again. */
 409         PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
 410         do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 411         read32(rank_address + 0x0);
 412
 413         /* 5. Perform 8 refresh cycles. Wait tRC each time. */
 414         PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
 415         do_ram_command(dev, RAM_COMMAND_CBR);
 416         for (i = 0; i < 8; i++) {
 417                 read32(rank_address + 0x20);
 418                 udelay(100);
 419         }
 420
 421         /* 6. Mode register set. */
 422         PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
 423         /* Safe value for now, BL=8, WR=5, CAS=4 */
 424         /*
 425          * (E)MRS values are from the BPG. No direct explanation is given, but
 426          * they should somehow conform to the JEDEC DDR2 SDRAM Specification
 427          * (JESD79-2C).
 428          */
 429         do_ram_command(dev, RAM_COMMAND_MRS);
 430         read32(rank_address + 0x002258); /* MRS command */
 431         read32(rank_address + 0x121c20); /* EMRS OCD Default */
 432         read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
 433
 434         /* 8. Normal operation */
 435         PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
 436         do_ram_command(dev, RAM_COMMAND_NORMAL);
 437         read32(rank_address + 0x30);
 438 }
 439
 440 /*
 441  * Support one DIMM with up to 2 ranks.
 442  */
 443 static void ddr_ram_setup(const struct mem_controller *ctrl)
 444 {
 445         u8 reg;
 446
 447         c7_cpu_setup(ctrl->d0f2);
 448         sdram_set_registers(ctrl);
 449         sdram_set_size(ctrl);
 450         sdram_enable(ctrl->d0f3, 0);
 451         reg = pci_read_config8(ctrl->d0f3, 0x41);
 452         if (reg != 0)
 453                 sdram_enable(ctrl->d0f3,
 454                              pci_read_config8(ctrl->d0f3, 0x40) << 26);
 455         sdram_set_post(ctrl);
 456 }