2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
28 #include "northbridge.h"
31 /* This is the main AGP device, and only one used when configured for AGP 2.0 */
32 static void agp_init(device_t dev)
36 /* Some of this may not be necessary (should be handled by the OS). */
37 printk_debug("Enabling AGP.\n");
39 /* Allow R/W access to AGP registers. */
40 pci_write_config8(dev, 0x4d, 0x15);
42 /* Setup PCI latency timer. */
43 pci_write_config8(dev, 0xd, 0x8);
46 * Set to AGP 3.0 Mode, which should theoretically render the rest of
47 * the registers set here pointless.
49 pci_write_config8(dev, 0x84, 0xb);
51 /* AGP Request Queue Size */
52 pci_write_config8(dev, 0x4a, 0x1f);
55 * AGP Hardware Support (default 0xc4)
56 * 7: AGP SBA Enable (1 to Enable)
59 * 4: Fast Write Enable
60 * 3: AGP8X Mode Enable
61 * 2: AGP4X Mode Enable
62 * 1: AGP2X Mode Enable
63 * 0: AGP1X Mode Enable
65 pci_write_config8(dev, 0x4b, 0xc4);
67 /* Enable AGP Backdoor */
68 pci_write_config8(dev, 0xb5, 0x03);
70 /* Set aperture to 32 MB. */
71 /* TODO: Use config option, explain how it works. */
72 pci_write_config32(dev, 0x94, 0x00010f38);
73 /* Set GART Table Base Address (31:12). */
74 pci_write_config32(dev, 0x98, (0x1558 << 12));
75 /* Set AGP Aperture Base. */
76 pci_write_config32(dev, 0x10, 0xf8000008);
78 /* Enable CPU/PMSTR GART Access. */
79 reg32 = pci_read_config8(dev, 0xbf);
81 pci_write_config8(dev, 0xbf, reg32);
83 /* Enable AGP Aperture. */
84 reg32 = pci_read_config32(dev, 0x94);
86 pci_write_config32(dev, 0x90, reg32);
89 pci_write_config8(dev, 0xbc, 0x21);
90 pci_write_config8(dev, 0xbd, 0xd2);
93 * AGP Pad, driving strength, and delay control. All this should be
94 * constant, seeing as the VGA controller is onboard.
96 pci_write_config8(dev, 0x40, 0xc7);
97 pci_write_config8(dev, 0x41, 0xdb);
98 pci_write_config8(dev, 0x42, 0x10);
99 pci_write_config8(dev, 0x43, 0xdb);
100 pci_write_config8(dev, 0x44, 0x24);
102 /* AGPC CKG Control */
103 pci_write_config8(dev, 0xc0, 0x02);
104 pci_write_config8(dev, 0xc1, 0x02);
107 static const struct device_operations agp_operations = {
108 .read_resources = cn700_noop,
109 .set_resources = pci_dev_set_resources,
110 .enable_resources = pci_dev_enable_resources,
115 static const struct pci_driver agp_driver __pci_driver = {
116 .ops = &agp_operations,
117 .vendor = PCI_VENDOR_ID_VIA,
118 .device = PCI_DEVICE_ID_VIA_CN700_AGP,
122 * This is the AGP 3.0 "bridge" @Bus 0 Device 1 Func 0. When using AGP 3.0, the
123 * config in this device takes presidence. We configure both just to be safe.
125 static void agp_bridge_init(device_t dev)
127 printk_debug("Setting up AGP bridge device\n");
129 pci_write_config16(dev, 0x4, 0x0007);
131 /* Secondary Bus Number */
132 pci_write_config8(dev, 0x19, 0x01);
133 /* Subordinate Bus Number */
134 pci_write_config8(dev, 0x1a, 0x01);
136 pci_write_config8(dev, 0x1c, 0xd0);
138 pci_write_config8(dev, 0x1d, 0xd0);
141 pci_write_config16(dev, 0x20, 0xfb00);
143 pci_write_config16(dev, 0x22, 0xfcf0);
144 /* Prefetchable Memory Base */
145 pci_write_config16(dev, 0x24, 0xf400);
146 /* Prefetchable Memory Limit */
147 pci_write_config16(dev, 0x26, 0xf7f0);
148 /* Enable VGA Compatible Memory/IO Range */
149 pci_write_config8(dev, 0x3e, 0x08);
151 /* Second PCI Bus Control (see datasheet) */
152 pci_write_config8(dev, 0x40, 0x83);
153 pci_write_config8(dev, 0x41, 0x43);
154 pci_write_config8(dev, 0x42, 0xe2);
155 pci_write_config8(dev, 0x43, 0x44);
156 pci_write_config8(dev, 0x44, 0x34);
157 pci_write_config8(dev, 0x45, 0x72);
160 static const struct device_operations agp_bridge_operations = {
161 .read_resources = cn700_noop,
162 .set_resources = pci_dev_set_resources,
163 .enable_resources = pci_bus_enable_resources,
164 .init = agp_bridge_init,
165 .scan_bus = pci_scan_bridge,
169 static const struct pci_driver agp_bridge_driver __pci_driver = {
170 .ops = &agp_bridge_operations,
171 .vendor = PCI_VENDOR_ID_VIA,
172 .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE,