2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Note: Some of the VGA control registers are located on the memory
23 * controller. Registers are set both in raminit.c and northbridge.c.
26 #include <console/console.h>
29 #include <device/device.h>
30 #include <device/pci.h>
31 #include <device/pci_ids.h>
36 #include <arch/interrupt.h>
38 #include "northbridge.h"
41 static int via_cn400_int15_handler(struct eregs *regs)
44 printk(BIOS_DEBUG, "via_cn400_int15_handler\n");
45 switch(regs->eax & 0xffff) {
50 regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
59 regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
64 regs->ebx= (regs->ebx & 0xffff0000) | 2;
65 regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
66 regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default
73 printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
80 static void vga_init(device_t dev)
84 mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler);
86 #undef OLD_BOCHS_METHOD
87 #ifdef OLD_BOCHS_METHOD
89 // XXX We might need more bios hooks in the f segment, but
90 // this way of copying the BOCHS BIOS does not work anymore.
91 // As soon as someone verifies that CN400 can init VGA, the
92 // code should be removed.
93 temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff);
94 printk(BIOS_DEBUG, "Copying BOCHS BIOS from 0x%08X to 0xf000\n", temp);
96 * Copy BOCHS BIOS from 4G-CONFIG_FALLBACK_SIZE-64k (in flash) to 0xf0000 (in RAM)
97 * This is for compatibility with the VGA ROM's BIOS callbacks.
99 //memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
100 memcpy((void *)0xf0000, (void *)temp, 0x10000);
103 /* Set memory rate to 200 MHz. */
104 outb(0x3d, CRTM_INDEX);
105 reg8 = inb(CRTM_DATA);
108 outb(0x3d, CRTM_INDEX);
109 outb(reg8, CRTM_DATA);
111 /* Set framebuffer size. */
112 reg8 = (CONFIG_VIDEO_MB / 4);
113 outb(0x39, SR_INDEX);
116 pci_write_config8(dev, 0x04, 0x07);
117 pci_write_config8(dev, 0x0d, 0x20);
118 pci_write_config32(dev, 0x10, 0xf0000008);
119 pci_write_config32(dev, 0x14, 0xf4000000);
121 printk(BIOS_DEBUG, "Initializing VGA...\n");
125 /* It's not clear if these need to be programmed before or after
126 * the VGA BIOS runs. Try both, clean up later. */
128 /* Set memory rate to 200 MHz (again). */
129 outb(0x3d, CRTM_INDEX);
130 reg8 = inb(CRTM_DATA);
133 outb(0x3d, CRTM_INDEX);
134 outb(reg8, CRTM_DATA);
136 /* Set framebuffer size (again). */
137 reg8 = (CONFIG_VIDEO_MB / 4);
138 outb(0x39, SR_INDEX);
141 #ifdef OLD_BOCHS_METHOD
142 /* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
143 memset((void *)0xf0000, 0, 0x10000);
149 printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));
151 for (i = 0 ; i < 16; i++)
153 printk(BIOS_SPEW, "%02X: ", i*16);
154 for (j = 0; j < 16; j++)
156 reg8 = pci_read_config8(dev, j+(i*16));
157 printk(BIOS_SPEW, "%02X ", reg8);
159 printk(BIOS_SPEW, "\n");
164 static const struct device_operations vga_operations = {
165 .read_resources = pci_dev_read_resources,
166 .set_resources = pci_dev_set_resources,
167 .enable_resources = pci_dev_enable_resources,
172 static const struct pci_driver vga_driver __pci_driver = {
173 .ops = &vga_operations,
174 .vendor = PCI_VENDOR_ID_VIA,
175 .device = PCI_DEVICE_ID_VIA_CN400_VGA,