src/northbridge/via/cn400/raminit.c

   1 /*
   2  * (C) Copyright 2005 Nick Barker <nick.barker9@btinternet.com>
   3  * (C) Copyright 2009 Jon Harrison <bothlyn@blueyonder.co.uk
   4  *
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 /*
  23   Automatically detect and set up ddr dram on the CN400 chipset.
  24   Assumes DDR400 memory as no attempt is made to clock
  25   the chipset down if slower memory is installed.
  26   So far tested on:
  27         512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
  28 */
  29 /* ported from Via VT8263 Code*/
  30
  31 #include <spd.h>
  32 #include <sdram_mode.h>
  33 #include <delay.h>
  34 #include <cpu/x86/mtrr.h>
  35 #include "cn400.h"
  36
  37 static void dimm_read(unsigned long bank,unsigned long x)
  38 {
  39         //unsigned long eax;
  40         volatile unsigned long y;
  41         //eax =  x;
  42         y = * (volatile unsigned long *) (x+ bank) ;
  43
  44 }
  45
  46
  47 static void print_val(char *str, int val)
  48 {
  49         print_debug(str);
  50         print_debug_hex8(val);
  51 }
  52
  53 /**
  54  * Configure the bus between the CPU and the northbridge. This might be able to
  55  * be moved to post-ram code in the future. For the most part, these registers
  56  * should not be messed around with. These are too complex to explain short of
  57  * copying the datasheets into the comments, but most of these values are from
  58  * the BIOS Porting Guide, so they should work on any board. If they don't,
  59  * try the values from your factory BIOS.
  60  *
  61  * TODO: Changing the DRAM frequency doesn't work (hard lockup).
  62  *
  63  * @param dev The northbridge's CPU Host Interface (D0F2).
  64  */
  65 static void c3_cpu_setup(device_t dev)
  66 {
  67         /* Host bus interface registers (D0F2 0x50-0x67) */
  68         /* Taken from CN700 and updated from running CN400 */
  69         uint8_t reg8;
  70
  71         /* Host Bus I/O Circuit (see datasheet) */
  72         /* Host Address Pullup/down Driving */
  73         pci_write_config8(dev, 0x70, 0x33);
  74         pci_write_config8(dev, 0x71, 0x44);
  75         pci_write_config8(dev, 0x72, 0x33);
  76         pci_write_config8(dev, 0x73, 0x44);
  77
  78         /* Output Delay Stagger Control */
  79         pci_write_config8(dev, 0x74, 0x70);
  80
  81         /* AGTL+ I/O Circuit */
  82         pci_write_config8(dev, 0x75, 0x08);
  83
  84         /* AGTL+ Compensation Status */
  85         pci_write_config8(dev, 0x76, 0x74);
  86
  87         /* AGTL+ Auto Compensation Offest */
  88         pci_write_config8(dev, 0x77, 0x00);
  89         pci_write_config8(dev, 0x78, 0x94);
  90
  91         /* Request phase control */
  92         pci_write_config8(dev, 0x50, 0xA8);
  93
  94         /* Line DRDY# Timing Control */
  95         pci_write_config8(dev, 0x60, 0x00);
  96         pci_write_config8(dev, 0x61, 0x00);
  97         pci_write_config8(dev, 0x62, 0x00);
  98
  99         /* QW DRDY# Timing Control */
 100         pci_write_config8(dev, 0x63, 0x00);
 101         pci_write_config8(dev, 0x64, 0x00);
 102         pci_write_config8(dev, 0x65, 0x00);
 103
 104         /* Read Line Burst DRDY# Timing Control */
 105         pci_write_config8(dev, 0x66, 0x00);
 106         pci_write_config8(dev, 0x67, 0x00);
 107
 108         /* CPU Interface Control */
 109         pci_write_config8(dev, 0x51, 0xFE);
 110         pci_write_config8(dev, 0x52, 0xEF);
 111
 112         /* Arbitration */
 113         pci_write_config8(dev, 0x53, 0x88);
 114
 115         /* Write Policy & Reorder Latecy */
 116         pci_write_config8(dev, 0x56, 0x00);
 117
 118         /* Delivery-Trigger Control */
 119         pci_write_config8(dev, 0x58, 0x00);
 120
 121         /* IPI Control */
 122         pci_write_config8(dev, 0x59, 0x30);
 123
 124         /* CPU Misc Control */
 125         pci_write_config8(dev, 0x5C, 0x00);
 126
 127         /* Write Policy */
 128         pci_write_config8(dev, 0x5d, 0xb2);
 129
 130         /* Bandwidth Timer */
 131         pci_write_config8(dev, 0x5e, 0x88);
 132
 133         /* CPU Miscellaneous Control */
 134         pci_write_config8(dev, 0x5f, 0xc7);
 135
 136         /* CPU Miscellaneous Control */
 137         pci_write_config8(dev, 0x55, 0x28);
 138         pci_write_config8(dev, 0x57, 0x69);
 139
 140         /* CPU Host Bus Final Setup */
 141         reg8 = pci_read_config8(dev, 0x54);
 142         reg8 |= 0x08;
 143         pci_write_config8(dev, 0x54, reg8);
 144
 145 }
 146
 147 static void ddr_ram_setup(void)
 148 {
 149         uint8_t b, c, bank, ma;
 150         uint16_t i;
 151         unsigned long bank_address;
 152
 153
 154         print_debug("CN400 RAM init starting\r\n");
 155
 156         pci_write_config8(ctrl.d0f7, 0x75, 0x08);
 157
 158
 159         /* No  Interleaving or Multi Page */
 160         pci_write_config8(ctrl.d0f3, 0x69, 0x00);
 161         pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
 162
 163 /*
 164     DRAM MA Map Type  Device 0  Fn3 Offset 50-51
 165
 166     Determine memory addressing based on the module's memory technology and
 167     arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
 168
 169     Bank 1/0 MA map type   50[7-5]
 170     Bank 1/0 command rate  50[4]
 171     Bank 3/2 MA map type   50[3-1]
 172     Bank 3/2 command rate  50[0]
 173
 174
 175     Read SPD byte 17, Number of banks on SDRAM device.
 176 */
 177         c = 0;
 178         b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
 179         //print_val("Detecting Memory\r\nNumber of Banks ",b);
 180
 181         // Only supporting 4 bank chips just now
 182         if( b == 4 ){
 183                 /*
 184                 Read SPD byte 3, Number of row addresses.
 185                 */
 186                 c = 0x01;
 187                 bank = 0x40;
 188                 b = smbus_read_byte(0x50, SPD_NUM_ROWS);
 189                 //print_val("\r\nNumber of Rows ", b);
 190
 191                 if( b >= 0x0d ){        // 256/512Mb
 192
 193                         if (b == 0x0e)
 194                                 bank = 0x48;
 195                         else
 196                                 bank = 0x44;
 197
 198                         /*
 199                         Read SPD byte 13, Primary DRAM width.
 200                         */
 201                         b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
 202                         //print_val("\r\nPrimary DRAM width", b);
 203                         if( b != 4 )   // not 64/128Mb (x4)
 204                                 c = 0x81;  // 256Mb
 205                 }
 206
 207                 /*
 208                 Read SPD byte 4, Number of column addresses.
 209                 */
 210                 b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
 211                 //print_val("\r\nNo Columns ",b);
 212                 if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
 213                 if( b == 9 ) c |= 0x40;           // 9 bit col addr
 214                 if( b == 8 ) c |= 0x20;           // 8 bit col addr
 215
 216                 //print_val("\r\nMA type ", c);
 217                 pci_write_config8(ctrl.d0f3, 0x50, c);
 218
 219         }
 220
 221         /* Disable Upper Banks */
 222         pci_write_config8(ctrl.d0f3, 0x51, 0x00);
 223
 224 /*      else
 225         {
 226                 die("DRAM module size is not supported by CN400\r\n");
 227         }
 228 */
 229
 230 /*
 231     DRAM bank size.  See 4.3.1 pg 35
 232
 233     5a->5d  set to end address for each bank.  1 bit == 32MB
 234     5a = bank 0
 235     5b = bank 0 + b1
 236     5c = bank 0 + b1 + b2
 237     5d = bank 0 + b1 + b2 + b3
 238 */
 239
 240         // Read SPD byte 31 Module bank density
 241         //c = 0;
 242         b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 243         if( b & 0x02 )
 244         {
 245                 c = 0x40;                                       // 2GB
 246                 bank |= 0x02;
 247         }
 248         else if( b & 0x01)
 249         {
 250                 c = 0x20;                                       // 1GB
 251                 if (bank == 0x48) bank |= 0x01;
 252                 else bank |= 0x03;
 253         }
 254         else if( b & 0x80)
 255         {
 256                 c = 0x10;                                       // 512MB
 257                 if (bank == 0x44) bank |= 0x02;
 258         }
 259         else if( b & 0x40)
 260         {
 261                 c = 0x08;                                       // 256MB
 262                 if (bank == 0x44) bank |= 0x01;
 263                 else bank |= 0x03;
 264         }
 265         else if( b & 0x20)
 266         {
 267                 c = 0x04;                                       // 128MB
 268                 if (bank == 0x40) bank |= 0x02;
 269         }
 270         else if( b & 0x10)
 271         {
 272                 c = 0x02;                                       // 64MB
 273                 bank |= 0x01;
 274         }
 275         else if( b & 0x08) c = 0x01;            // 32MB
 276         else c = 0x01;                          // Error, use default
 277
 278         // set bank zero size
 279         pci_write_config8(ctrl.d0f3, 0x40, c);
 280
 281         // SPD byte 5  # of physical banks
 282         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
 283
 284         //print_val("\r\nNo Physical Banks ",b);
 285         if( b == 2)
 286         {
 287                 c <<=1;
 288                 bank |= 0x80;
 289         }
 290 /*      else
 291         {
 292                 die("Only a single DIMM is supported by EPIA-N(L)\r\n");
 293         }
 294 */
 295         // set banks 1,2,3...
 296         pci_write_config8(ctrl.d0f3, 0x41,c);
 297         pci_write_config8(ctrl.d0f3, 0x42,c);
 298         pci_write_config8(ctrl.d0f3, 0x43,c);
 299         pci_write_config8(ctrl.d0f3, 0x44,c);
 300         pci_write_config8(ctrl.d0f3, 0x45,c);
 301         pci_write_config8(ctrl.d0f3, 0x46,c);
 302         pci_write_config8(ctrl.d0f3, 0x47,c);
 303
 304         /* Top Rank Address Mirrored to the South Bridge */
 305         /* over the VLink                                                                */
 306         pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
 307
 308         ma = bank;
 309
 310         /* Read SPD byte 18 CAS Latency */
 311         b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
 312 /*      print_debug("\r\nCAS Supported ");
 313         if(b & 0x04)
 314                 print_debug("2 ");
 315         if(b & 0x08)
 316                 print_debug("2.5 ");
 317         if(b & 0x10)
 318                 print_debug("3");
 319
 320         c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 321         print_val("\r\nCycle time at CL X     (nS)", c);
 322         c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
 323         print_val("\r\nCycle time at CL X-0.5 (nS)", c);
 324         c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
 325         print_val("\r\nCycle time at CL X-1   (nS)", c);
 326 */
 327         /* Scaling of Cycle Time SPD data */
 328         /* 7      4 3       0             */
 329         /*    ns     x0.1ns               */
 330         bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 331
 332         if( b & 0x10 ){             // DDR offering optional CAS 3
 333                 //print_debug("\r\nStarting at CAS 3");
 334                 c = 0x30;
 335                 /* see if we can better it */
 336                 if( b & 0x08 ){     // DDR mandatory CAS 2.5
 337                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
 338                                 //print_debug("\r\nWe can do CAS 2.5");
 339                                 c = 0x20;
 340                         }
 341                 }
 342                 if( b & 0x04 ){     // DDR mandatory CAS 2
 343                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
 344                                 //print_debug("\r\nWe can do CAS 2");
 345                                 c = 0x10;
 346                         }
 347                 }
 348         }else{                     // no optional CAS values just 2 & 2.5
 349                 //print_debug("\r\nStarting at CAS 2.5");
 350                 c = 0x20;          // assume CAS 2.5
 351                 if( b & 0x04){      // Should always happen
 352                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
 353                                 //print_debug("\r\nWe can do CAS 2");
 354                                 c = 0x10;
 355                         }
 356                 }
 357         }
 358
 359         /* Scale DRAM Cycle Time to tRP/tRCD */
 360         /* 7      2 1       0             */
 361         /*    ns     x0.25ns               */
 362         if ( bank <= 0x50 ) bank = 0x14;
 363         else if (bank <= 0x60) bank = 0x18;
 364         else bank = 0x1E;
 365
 366 /*
 367     DRAM Timing  Device 0  Fn 3 Offset 56
 368
 369     RAS Pulse width 56[7,6]
 370     CAS Latency     56[5,4]
 371     Row pre-charge  56[1,0]
 372
 373          SDR  DDR
 374       00  1T   -
 375       01  2T   2T
 376       10  3T   2.5T
 377       11  -    3T
 378
 379     RAS/CAS delay   56[3,2]
 380
 381     Determine row pre-charge time (tRP)
 382
 383
 384     Read SPD byte 27, min row pre-charge time.
 385 */
 386
 387         b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
 388
 389         //print_val("\r\ntRP ",b);
 390         if ( b >= (5 * bank)) {
 391                 c |= 0x03;              // set tRP = 5T
 392         }
 393         else if ( b >= (4 * bank)) {
 394                 c |= 0x02;              // set tRP = 4T
 395         }
 396         else if ( b >= (3 * bank)) {
 397                 c |= 0x01;              // set tRP = 3T
 398         }
 399
 400 /*
 401     Determine RAS to CAS delay (tRCD)
 402
 403     Read SPD byte 29, min row pre-charge time.
 404 */
 405
 406         b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
 407         //print_val("\r\ntRCD ",b);
 408
 409         if ( b >= (5 * bank)) c |= 0x0C;                // set tRCD = 5T
 410         else if ( b >= (4 * bank)) c |= 0x08;   // set tRCD = 4T
 411         else if ( b >= (3 * bank)) c |= 0x04;   // set tRCD = 3T
 412
 413 /*
 414     Determine RAS pulse width (tRAS)
 415
 416
 417     Read SPD byte 30, device min active to pre-charge time.
 418 */
 419
 420         /* tRAS is in whole ns */
 421         bank = bank >> 2;
 422
 423         b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 424         //print_val("\r\ntRAS ",b);
 425         //print_val("\r\nBank ", bank);
 426         if ( b >= (9 * bank)) c |= 0xC0;                // set tRAS = 9T
 427         else if ( b >= (8 * bank)) c |= 0x80;   // set tRAS = 8T
 428         else if ( b >= (7 * bank)) c |= 0x40;   // set tRAS = 7T
 429
 430         /* Write DRAM Timing All Banks I */
 431         pci_write_config8(ctrl.d0f3, 0x56, c);
 432
 433         /* TWrite DRAM Timing All Banks II */
 434         pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
 435
 436         /* DRAM arbitration timer */
 437         pci_write_config8(ctrl.d0f3, 0x65, 0x99);
 438
 439 /*
 440     DRAM Clock  Device 0 Fn 3 Offset 68
 441 */
 442         bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 443
 444         /* Setup DRAM Cycle Time */
 445         if ( bank <= 0x50 )
 446         {
 447                 /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
 448                 /* This sets to 133MHz FSB / DDR400. */
 449                 pci_write_config8(ctrl.d0f3, 0x68, 0x85);
 450         }
 451         else if (bank <= 0x60)
 452         {
 453                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 454                 /* 133MHz FSB / DDR333.  See also c3_cpu_setup */
 455                 pci_write_config8(ctrl.d0f3, 0x68, 0x81);
 456         }
 457         else
 458         {
 459                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 460                 /* 133MHz FSB / DDR266.  See also c3_cpu_setup */
 461                 pci_write_config8(ctrl.d0f3, 0x68, 0x80);
 462         }
 463
 464         /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
 465         udelay(200);
 466
 467 /*
 468     Determine bank interleave
 469
 470     Read SPD byte 17, Number of banks on SDRAM device.
 471 */
 472         c = 0x0F;
 473         b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
 474         if( b == 4) c |= 0x80;
 475         else if (b == 2) c |= 0x40;
 476
 477         /* 4-Way Interleave With Multi-Paging (From Running System)*/
 478         pci_write_config8(ctrl.d0f3, 0x69, c);
 479
 480         /*DRAM Controller Internal Options */
 481         pci_write_config8(ctrl.d0f3, 0x54, 0x01);
 482
 483         /* DRAM Arbitration Control */
 484         pci_write_config8(ctrl.d0f3, 0x66, 0x82);
 485
 486         /* DRAM Control */
 487         pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
 488
 489         /* Disable refresh for now */
 490         pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
 491
 492         /* DDR Clock Gen Duty Cycle Control */
 493         pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
 494
 495
 496         /* DRAM Clock Control */
 497         pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
 498
 499         /* DRAM Bus Turn-Around Setting */
 500         pci_write_config8(ctrl.d0f3, 0x60, 0x01);
 501
 502         /* Disable DRAM refresh */
 503         pci_write_config8(ctrl.d0f3,0x6a,0x0);
 504
 505
 506         /* Memory Pads Driving and Range Select */
 507         pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
 508         pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
 509         pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
 510
 511         /* DRAM signal timing control */
 512         pci_write_config8(ctrl.d0f3, 0x74, 0x99);
 513         pci_write_config8(ctrl.d0f3, 0x76, 0x09);
 514         pci_write_config8(ctrl.d0f3, 0x77, 0x12);
 515
 516         pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
 517         pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
 518         pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
 519         pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
 520         pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
 521
 522
 523         /* SPD byte 5  # of physical banks */
 524         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
 525         c = b | 0x40;
 526
 527         pci_write_config8(ctrl.d0f3, 0xb0, c);
 528
 529         /* Set RAM Decode method */
 530         pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
 531
 532         /* Enable DIMM Ranks */
 533         pci_write_config8(ctrl.d0f3, 0x48, ma);
 534         udelay(200);
 535
 536         c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
 537         c &= 0x08;
 538         if ( c == 0x08 )
 539         {
 540                 print_debug("Setting Burst Length 8\r\n");
 541                 /*
 542                 CPU Frequency  Device 0 Function 2 Offset 54
 543
 544                         CPU FSB Operating Frequency (bits 7:5)
 545                         000 : 100MHz    001 : 133MHz
 546                         010 : 200MHz
 547                                 011->111 : Reserved
 548
 549                         SDRAM BL8 (4)
 550
 551                         Don't change Frequency from power up defaults
 552                         This seems to lockup the RAM interface
 553                 */
 554                 c = pci_read_config8(ctrl.d0f2, 0x54);
 555                 c |= 0x10;
 556                 pci_write_config8(ctrl.d0f2, 0x54, c);
 557                 i = 0x008;              // Used later to set SDRAM MSR
 558         }
 559
 560
 561         for( bank = 0 , bank_address=0; bank <= b ; bank++) {
 562 /*
 563     DDR init described in Via VT8623 BIOS Porting Guide.  Pg 28 (4.2.3.1)
 564 */
 565
 566                 /* NOP command enable */
 567                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 568                 c &= 0xf8;              /* Clear bits 2-0. */
 569                 c |= RAM_COMMAND_NOP;
 570                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 571
 572                 /* read a double word from any address of the dimm */
 573                 dimm_read(bank_address,0x1f000);
 574                 //udelay(200);
 575
 576                 /* All bank precharge Command Enable */
 577                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 578                 c &= 0xf8;              /* Clear bits 2-0. */
 579                 c |= RAM_COMMAND_PRECHARGE;
 580                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 581                 dimm_read(bank_address,0x1f000);
 582
 583
 584                 /* MSR Enable Low DIMM*/
 585                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 586                 c &= 0xf8;              /* Clear bits 2-0. */
 587                 c |= RAM_COMMAND_MSR_LOW;
 588                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 589                 /* TODO: Bank Addressing for Different Numbers of Row Addresses */
 590                 dimm_read(bank_address,0x2000);
 591                 udelay(1);
 592                 dimm_read(bank_address,0x800);
 593                 udelay(1);
 594
 595                 /* All banks precharge Command Enable */
 596                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 597                 c &= 0xf8;              /* Clear bits 2-0. */
 598                 c |= RAM_COMMAND_PRECHARGE;
 599                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 600                 dimm_read(bank_address,0x1f200);
 601
 602                 /* CBR Cycle Enable */
 603                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 604                 c &= 0xf8;              /* Clear bits 2-0. */
 605                 c |= RAM_COMMAND_CBR;
 606                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 607
 608                 /* Read 8 times */
 609                 for (c=0;c<8;c++) {
 610                         dimm_read(bank_address,0x1f300);
 611                         udelay(100);
 612                 }
 613
 614                 /* MSR Enable */
 615                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 616                 c &= 0xf8;              /* Clear bits 2-0. */
 617                 c |= RAM_COMMAND_MSR_LOW;
 618                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 619
 620
 621 /*
 622     Mode Register Definition
 623     with adjustement so that address calculation is correct - 64 bit technology, therefore
 624     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
 625     to DIMM as a row or column address.
 626
 627     MR[9-7]   CAS Latency
 628     MR[6]     Burst Type 0 = sequential, 1 = interleaved
 629     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
 630     MR[0-2]   dont care
 631
 632     CAS Latency
 633     000       reserved
 634     001       reserved
 635     010       2
 636     011       3
 637     100       reserved
 638     101       1.5
 639     110       2.5
 640     111       reserved
 641
 642     CAS 2     0101011000 = 0x158
 643     CAS 2.5   1101011000 = 0x358
 644     CAS 3     0111011000 = 0x1d8
 645
 646 */
 647                 c = pci_read_config8(ctrl.d0f3, 0x56);
 648                 if( (c & 0x30) == 0x10 )
 649                         dimm_read(bank_address,(0x150 + i));
 650                 else if((c & 0x30) == 0x20 )
 651                         dimm_read(bank_address,(0x350 + i));
 652                 else
 653                         dimm_read(bank_address,(0x1d0 + i));
 654
 655
 656                 /* Normal SDRAM Mode */
 657                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 658                 c &= 0xf8;              /* Clear bits 2-0. */
 659                 c |= RAM_COMMAND_NORMAL;
 660                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 661
 662                 bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
 663         } // end of for each bank
 664
 665
 666         /* Set DRAM DQS Output Control */
 667         pci_write_config8(ctrl.d0f3, 0x79, 0x11);
 668
 669         /* Set DQS A/B Input delay to defaults */
 670         pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
 671         pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
 672
 673         /* DQS Duty Cycle Control */
 674         pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 675
 676         /* SPD byte 5  # of physical banks */
 677         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
 678
 679         /* determine low bond */
 680         if( b == 2)
 681                 bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
 682         else
 683                 bank_address = 0;
 684
 685         for(i = 0x30 ; i < 0x0ff; i++){
 686                 pci_write_config8(ctrl.d0f3,0x70,i);
 687                 // clear
 688                 *(volatile unsigned long*)(0x4000) = 0;
 689                 *(volatile unsigned long*)(0x4100+bank_address) = 0;
 690                 *(volatile unsigned long*)(0x4200) = 0;
 691                 *(volatile unsigned long*)(0x4300+bank_address) = 0;
 692                 *(volatile unsigned long*)(0x4400) = 0;
 693                 *(volatile unsigned long*)(0x4500+bank_address) = 0;
 694
 695                 // fill
 696                 *(volatile unsigned long*)(0x4000) = 0x12345678;
 697                 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
 698                 *(volatile unsigned long*)(0x4200) = 0x78123456;
 699                 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
 700                 *(volatile unsigned long*)(0x4400) = 0x56781234;
 701                 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
 702
 703                         // verify
 704                 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
 705                         continue;
 706
 707                 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
 708                         continue;
 709
 710                 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
 711                         continue;
 712
 713                 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
 714                         continue;
 715
 716                 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
 717                         continue;
 718
 719                 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
 720                         continue;
 721
 722                 // if everything verified then found low bond
 723                 break;
 724
 725         }
 726         print_val("\r\nLow Bond ",i);
 727         if( i < 0xff ){
 728                 c = i++;
 729                 for(  ; i <0xff ; i++){
 730                         pci_write_config8(ctrl.d0f3,0x70, i);
 731                         // clear
 732                         *(volatile unsigned long*)(0x8000) = 0;
 733                         *(volatile unsigned long*)(0x8100+bank_address) = 0;
 734                         *(volatile unsigned long*)(0x8200) = 0x0;
 735                         *(volatile unsigned long*)(0x8300+bank_address) = 0;
 736                         *(volatile unsigned long*)(0x8400) = 0x0;
 737                         *(volatile unsigned long*)(0x8500+bank_address) = 0;
 738
 739                         // fill
 740                         *(volatile unsigned long*)(0x8000) = 0x12345678;
 741                         *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
 742                         *(volatile unsigned long*)(0x8200) = 0x78123456;
 743                         *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
 744                         *(volatile unsigned long*)(0x8400) = 0x56781234;
 745                         *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
 746
 747                         // verify
 748                         if( *(volatile unsigned long*)(0x8000) != 0x12345678)
 749                                 break;
 750
 751                         if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
 752                                 break;
 753
 754                         if( *(volatile unsigned long*)(0x8200) != 0x78123456)
 755                                 break;
 756
 757                         if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
 758                                 break;
 759
 760                         if( *(volatile unsigned long*)(0x8400) != 0x56781234)
 761                                 break;
 762
 763                         if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
 764                                 break;
 765
 766                 }
 767                 print_val("  High Bond ",i);
 768                 c = ((i - c)<<1)/3 + c;
 769                 print_val("  Setting DQS delay",c);
 770                 print_debug("\r\n");
 771                 pci_write_config8(ctrl.d0f3,0x70,c);
 772         }else{
 773                 pci_write_config8(ctrl.d0f3,0x70,0x67);
 774         }
 775
 776         /* Set DQS ChA Data Output Delay to the default */
 777         pci_write_config8(ctrl.d0f3, 0x71, 0x65);
 778
 779         /* Set Ch B DQS Output Delays */
 780         pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
 781         pci_write_config8(ctrl.d0f3, 0x73, 0x29);
 782
 783         pci_write_config8(ctrl.d0f3, 0x78, 0x03);
 784
 785         /* Mystery Value */
 786         pci_write_config8(ctrl.d0f3, 0x67, 0x50);
 787
 788         /* Enable Toggle Limiting */
 789         pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
 790
 791 /*
 792     DRAM refresh rate  Device 0 F3 Offset 6a
 793         TODO :: Fix for different DRAM technologies
 794         other than 512Mb and DRAM Freq
 795     Units of 16 DRAM clock cycles - 1.
 796 */
 797         //c = pci_read_config8(ctrl.d0f3, 0x68);
 798         //c &= 0x07;
 799         //b = smbus_read_byte(0x50, SPD_REFRESH);
 800         //print_val("SPD_REFRESH = ", b);
 801
 802         pci_write_config8(ctrl.d0f3,0x6a,0x65);
 803
 804         /* SMM and APIC decoding, we do not use SMM */
 805         b = 0x29;
 806         pci_write_config8(ctrl.d0f3, 0x86, b);
 807         /* SMM and APIC decoding mirror */
 808         pci_write_config8(ctrl.d0f7, 0xe6, b);
 809
 810         /* Open Up the Rest of the Shadow RAM */
 811         pci_write_config8(ctrl.d0f3,0x80,0xff);
 812         pci_write_config8(ctrl.d0f3,0x81,0xff);
 813
 814         /* pci */
 815         pci_write_config8(ctrl.d0f7,0x70,0x82);
 816         pci_write_config8(ctrl.d0f7,0x73,0x01);
 817         pci_write_config8(ctrl.d0f7,0x76,0x50);
 818
 819         pci_write_config8(ctrl.d0f7,0x71,0xc8);
 820
 821
 822         /* VGA device. */
 823         pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 824         pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
 825     print_debug("CN400 raminit.c done\r\n");
 826 }