src/northbridge/via/cn400/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
   5  * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 /*
  23   Automatically detect and set up ddr dram on the CN400 chipset.
  24   Assumes DDR400 memory as no attempt is made to clock
  25   the chipset down if slower memory is installed.
  26   So far tested on:
  27         512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
  28 */
  29 /* ported from Via VT8263 Code*/
  30
  31 #include <spd.h>
  32 #include <delay.h>
  33 #include <cpu/x86/mtrr.h>
  34 #include "cn400.h"
  35
  36 static void dimm_read(unsigned long bank,unsigned long x)
  37 {
  38         //unsigned long eax;
  39         volatile unsigned long y;
  40         //eax =  x;
  41         y = * (volatile unsigned long *) (x+ bank) ;
  42
  43 }
  44
  45
  46 static void print_val(char *str, int val)
  47 {
  48         print_debug(str);
  49         print_debug_hex8(val);
  50 }
  51
  52 /**
  53  * Configure the bus between the CPU and the northbridge. This might be able to
  54  * be moved to post-ram code in the future. For the most part, these registers
  55  * should not be messed around with. These are too complex to explain short of
  56  * copying the datasheets into the comments, but most of these values are from
  57  * the BIOS Porting Guide, so they should work on any board. If they don't,
  58  * try the values from your factory BIOS.
  59  *
  60  * TODO: Changing the DRAM frequency doesn't work (hard lockup).
  61  *
  62  * @param dev The northbridge's CPU Host Interface (D0F2).
  63  */
  64 static void c3_cpu_setup(device_t dev)
  65 {
  66         /* Host bus interface registers (D0F2 0x50-0x67) */
  67         /* Taken from CN700 and updated from running CN400 */
  68         uint8_t reg8;
  69
  70         /* Host Bus I/O Circuit (see datasheet) */
  71         /* Host Address Pullup/down Driving */
  72         pci_write_config8(dev, 0x70, 0x33);
  73         pci_write_config8(dev, 0x71, 0x44);
  74         pci_write_config8(dev, 0x72, 0x33);
  75         pci_write_config8(dev, 0x73, 0x44);
  76
  77         /* Output Delay Stagger Control */
  78         pci_write_config8(dev, 0x74, 0x70);
  79
  80         /* AGTL+ I/O Circuit */
  81         pci_write_config8(dev, 0x75, 0x08);
  82
  83         /* AGTL+ Compensation Status */
  84         pci_write_config8(dev, 0x76, 0x74);
  85
  86         /* AGTL+ Auto Compensation Offest */
  87         pci_write_config8(dev, 0x77, 0x00);
  88         pci_write_config8(dev, 0x78, 0x94);
  89
  90         /* Request phase control */
  91         pci_write_config8(dev, 0x50, 0xA8);
  92
  93         /* Line DRDY# Timing Control */
  94         pci_write_config8(dev, 0x60, 0x00);
  95         pci_write_config8(dev, 0x61, 0x00);
  96         pci_write_config8(dev, 0x62, 0x00);
  97
  98         /* QW DRDY# Timing Control */
  99         pci_write_config8(dev, 0x63, 0x00);
 100         pci_write_config8(dev, 0x64, 0x00);
 101         pci_write_config8(dev, 0x65, 0x00);
 102
 103         /* Read Line Burst DRDY# Timing Control */
 104         pci_write_config8(dev, 0x66, 0x00);
 105         pci_write_config8(dev, 0x67, 0x00);
 106
 107         /* CPU Interface Control */
 108         pci_write_config8(dev, 0x51, 0xFE);
 109         pci_write_config8(dev, 0x52, 0xEF);
 110
 111         /* Arbitration */
 112         pci_write_config8(dev, 0x53, 0x88);
 113
 114         /* Write Policy & Reorder Latecy */
 115         pci_write_config8(dev, 0x56, 0x00);
 116
 117         /* Delivery-Trigger Control */
 118         pci_write_config8(dev, 0x58, 0x00);
 119
 120         /* IPI Control */
 121         pci_write_config8(dev, 0x59, 0x30);
 122
 123         /* CPU Misc Control */
 124         pci_write_config8(dev, 0x5C, 0x00);
 125
 126         /* Write Policy */
 127         pci_write_config8(dev, 0x5d, 0xb2);
 128
 129         /* Bandwidth Timer */
 130         pci_write_config8(dev, 0x5e, 0x88);
 131
 132         /* CPU Miscellaneous Control */
 133         pci_write_config8(dev, 0x5f, 0xc7);
 134
 135         /* CPU Miscellaneous Control */
 136         pci_write_config8(dev, 0x55, 0x28);
 137         pci_write_config8(dev, 0x57, 0x69);
 138
 139         /* CPU Host Bus Final Setup */
 140         reg8 = pci_read_config8(dev, 0x54);
 141         reg8 |= 0x08;
 142         pci_write_config8(dev, 0x54, reg8);
 143
 144 }
 145
 146 static void ddr_ram_setup(void)
 147 {
 148         uint8_t b, c, bank, ma;
 149         uint16_t i;
 150         unsigned long bank_address;
 151
 152
 153         print_debug("CN400 RAM init starting\n");
 154
 155         pci_write_config8(ctrl.d0f7, 0x75, 0x08);
 156
 157
 158         /* No  Interleaving or Multi Page */
 159         pci_write_config8(ctrl.d0f3, 0x69, 0x00);
 160         pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
 161
 162 /*
 163     DRAM MA Map Type  Device 0  Fn3 Offset 50-51
 164
 165     Determine memory addressing based on the module's memory technology and
 166     arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
 167
 168     Bank 1/0 MA map type   50[7-5]
 169     Bank 1/0 command rate  50[4]
 170     Bank 3/2 MA map type   50[3-1]
 171     Bank 3/2 command rate  50[0]
 172
 173
 174     Read SPD byte 17, Number of banks on SDRAM device.
 175 */
 176         c = 0;
 177         b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
 178         //print_val("Detecting Memory\nNumber of Banks ",b);
 179
 180         // Only supporting 4 bank chips just now
 181         if( b == 4 ){
 182                 /*
 183                 Read SPD byte 3, Number of row addresses.
 184                 */
 185                 c = 0x01;
 186                 bank = 0x40;
 187                 b = smbus_read_byte(0x50, SPD_NUM_ROWS);
 188                 //print_val("\nNumber of Rows ", b);
 189
 190                 if( b >= 0x0d ){        // 256/512Mb
 191
 192                         if (b == 0x0e)
 193                                 bank = 0x48;
 194                         else
 195                                 bank = 0x44;
 196
 197                         /*
 198                         Read SPD byte 13, Primary DRAM width.
 199                         */
 200                         b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
 201                         //print_val("\nPrimary DRAM width", b);
 202                         if( b != 4 )   // not 64/128Mb (x4)
 203                                 c = 0x81;  // 256Mb
 204                 }
 205
 206                 /*
 207                 Read SPD byte 4, Number of column addresses.
 208                 */
 209                 b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
 210                 //print_val("\nNo Columns ",b);
 211                 if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
 212                 if( b == 9 ) c |= 0x40;           // 9 bit col addr
 213                 if( b == 8 ) c |= 0x20;           // 8 bit col addr
 214
 215                 //print_val("\nMA type ", c);
 216                 pci_write_config8(ctrl.d0f3, 0x50, c);
 217
 218         }
 219
 220         /* Disable Upper Banks */
 221         pci_write_config8(ctrl.d0f3, 0x51, 0x00);
 222
 223 /*      else
 224         {
 225                 die("DRAM module size is not supported by CN400\n");
 226         }
 227 */
 228
 229 /*
 230     DRAM bank size.  See 4.3.1 pg 35
 231
 232     5a->5d  set to end address for each bank.  1 bit == 32MB
 233     5a = bank 0
 234     5b = bank 0 + b1
 235     5c = bank 0 + b1 + b2
 236     5d = bank 0 + b1 + b2 + b3
 237 */
 238
 239         // Read SPD byte 31 Module bank density
 240         //c = 0;
 241         b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 242         if( b & 0x02 )
 243         {
 244                 c = 0x40;                                       // 2GB
 245                 bank |= 0x02;
 246         }
 247         else if( b & 0x01)
 248         {
 249                 c = 0x20;                                       // 1GB
 250                 if (bank == 0x48) bank |= 0x01;
 251                 else bank |= 0x03;
 252         }
 253         else if( b & 0x80)
 254         {
 255                 c = 0x10;                                       // 512MB
 256                 if (bank == 0x44) bank |= 0x02;
 257         }
 258         else if( b & 0x40)
 259         {
 260                 c = 0x08;                                       // 256MB
 261                 if (bank == 0x44) bank |= 0x01;
 262                 else bank |= 0x03;
 263         }
 264         else if( b & 0x20)
 265         {
 266                 c = 0x04;                                       // 128MB
 267                 if (bank == 0x40) bank |= 0x02;
 268         }
 269         else if( b & 0x10)
 270         {
 271                 c = 0x02;                                       // 64MB
 272                 bank |= 0x01;
 273         }
 274         else if( b & 0x08) c = 0x01;            // 32MB
 275         else c = 0x01;                          // Error, use default
 276
 277         // set bank zero size
 278         pci_write_config8(ctrl.d0f3, 0x40, c);
 279
 280         // SPD byte 5  # of physical banks
 281         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
 282
 283         //print_val("\nNo Physical Banks ",b);
 284         if( b == 2)
 285         {
 286                 c <<=1;
 287                 bank |= 0x80;
 288         }
 289 /*      else
 290         {
 291                 die("Only a single DIMM is supported by EPIA-N(L)\n");
 292         }
 293 */
 294         // set banks 1,2,3...
 295         pci_write_config8(ctrl.d0f3, 0x41,c);
 296         pci_write_config8(ctrl.d0f3, 0x42,c);
 297         pci_write_config8(ctrl.d0f3, 0x43,c);
 298         pci_write_config8(ctrl.d0f3, 0x44,c);
 299         pci_write_config8(ctrl.d0f3, 0x45,c);
 300         pci_write_config8(ctrl.d0f3, 0x46,c);
 301         pci_write_config8(ctrl.d0f3, 0x47,c);
 302
 303         /* Top Rank Address Mirrored to the South Bridge */
 304         /* over the VLink                                                                */
 305         pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
 306
 307         ma = bank;
 308
 309         /* Read SPD byte 18 CAS Latency */
 310         b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
 311 /*      print_debug("\nCAS Supported ");
 312         if(b & 0x04)
 313                 print_debug("2 ");
 314         if(b & 0x08)
 315                 print_debug("2.5 ");
 316         if(b & 0x10)
 317                 print_debug("3");
 318
 319         c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 320         print_val("\nCycle time at CL X     (nS)", c);
 321         c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
 322         print_val("\nCycle time at CL X-0.5 (nS)", c);
 323         c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
 324         print_val("\nCycle time at CL X-1   (nS)", c);
 325 */
 326         /* Scaling of Cycle Time SPD data */
 327         /* 7      4 3       0             */
 328         /*    ns     x0.1ns               */
 329         bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 330
 331         if( b & 0x10 ){             // DDR offering optional CAS 3
 332                 //print_debug("\nStarting at CAS 3");
 333                 c = 0x30;
 334                 /* see if we can better it */
 335                 if( b & 0x08 ){     // DDR mandatory CAS 2.5
 336                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
 337                                 //print_debug("\nWe can do CAS 2.5");
 338                                 c = 0x20;
 339                         }
 340                 }
 341                 if( b & 0x04 ){     // DDR mandatory CAS 2
 342                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
 343                                 //print_debug("\nWe can do CAS 2");
 344                                 c = 0x10;
 345                         }
 346                 }
 347         }else{                     // no optional CAS values just 2 & 2.5
 348                 //print_debug("\nStarting at CAS 2.5");
 349                 c = 0x20;          // assume CAS 2.5
 350                 if( b & 0x04){      // Should always happen
 351                         if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
 352                                 //print_debug("\nWe can do CAS 2");
 353                                 c = 0x10;
 354                         }
 355                 }
 356         }
 357
 358         /* Scale DRAM Cycle Time to tRP/tRCD */
 359         /* 7      2 1       0             */
 360         /*    ns     x0.25ns               */
 361         if ( bank <= 0x50 ) bank = 0x14;
 362         else if (bank <= 0x60) bank = 0x18;
 363         else bank = 0x1E;
 364
 365 /*
 366     DRAM Timing  Device 0  Fn 3 Offset 56
 367
 368     RAS Pulse width 56[7,6]
 369     CAS Latency     56[5,4]
 370     Row pre-charge  56[1,0]
 371
 372          SDR  DDR
 373       00  1T   -
 374       01  2T   2T
 375       10  3T   2.5T
 376       11  -    3T
 377
 378     RAS/CAS delay   56[3,2]
 379
 380     Determine row pre-charge time (tRP)
 381
 382
 383     Read SPD byte 27, min row pre-charge time.
 384 */
 385
 386         b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
 387
 388         //print_val("\ntRP ",b);
 389         if ( b >= (5 * bank)) {
 390                 c |= 0x03;              // set tRP = 5T
 391         }
 392         else if ( b >= (4 * bank)) {
 393                 c |= 0x02;              // set tRP = 4T
 394         }
 395         else if ( b >= (3 * bank)) {
 396                 c |= 0x01;              // set tRP = 3T
 397         }
 398
 399 /*
 400     Determine RAS to CAS delay (tRCD)
 401
 402     Read SPD byte 29, min row pre-charge time.
 403 */
 404
 405         b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
 406         //print_val("\ntRCD ",b);
 407
 408         if ( b >= (5 * bank)) c |= 0x0C;                // set tRCD = 5T
 409         else if ( b >= (4 * bank)) c |= 0x08;   // set tRCD = 4T
 410         else if ( b >= (3 * bank)) c |= 0x04;   // set tRCD = 3T
 411
 412 /*
 413     Determine RAS pulse width (tRAS)
 414
 415
 416     Read SPD byte 30, device min active to pre-charge time.
 417 */
 418
 419         /* tRAS is in whole ns */
 420         bank = bank >> 2;
 421
 422         b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 423         //print_val("\ntRAS ",b);
 424         //print_val("\nBank ", bank);
 425         if ( b >= (9 * bank)) c |= 0xC0;                // set tRAS = 9T
 426         else if ( b >= (8 * bank)) c |= 0x80;   // set tRAS = 8T
 427         else if ( b >= (7 * bank)) c |= 0x40;   // set tRAS = 7T
 428
 429         /* Write DRAM Timing All Banks I */
 430         pci_write_config8(ctrl.d0f3, 0x56, c);
 431
 432         /* TWrite DRAM Timing All Banks II */
 433         pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
 434
 435         /* DRAM arbitration timer */
 436         pci_write_config8(ctrl.d0f3, 0x65, 0x99);
 437
 438 /*
 439     DRAM Clock  Device 0 Fn 3 Offset 68
 440 */
 441         bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 442
 443         /* Setup DRAM Cycle Time */
 444         if ( bank <= 0x50 )
 445         {
 446                 /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
 447                 /* This sets to 133MHz FSB / DDR400. */
 448                 pci_write_config8(ctrl.d0f3, 0x68, 0x85);
 449         }
 450         else if (bank <= 0x60)
 451         {
 452                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 453                 /* 133MHz FSB / DDR333.  See also c3_cpu_setup */
 454                 pci_write_config8(ctrl.d0f3, 0x68, 0x81);
 455         }
 456         else
 457         {
 458                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 459                 /* 133MHz FSB / DDR266.  See also c3_cpu_setup */
 460                 pci_write_config8(ctrl.d0f3, 0x68, 0x80);
 461         }
 462
 463         /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
 464         udelay(200);
 465
 466 /*
 467     Determine bank interleave
 468
 469     Read SPD byte 17, Number of banks on SDRAM device.
 470 */
 471         c = 0x0F;
 472         b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
 473         if( b == 4) c |= 0x80;
 474         else if (b == 2) c |= 0x40;
 475
 476         /* 4-Way Interleave With Multi-Paging (From Running System)*/
 477         pci_write_config8(ctrl.d0f3, 0x69, c);
 478
 479         /*DRAM Controller Internal Options */
 480         pci_write_config8(ctrl.d0f3, 0x54, 0x01);
 481
 482         /* DRAM Arbitration Control */
 483         pci_write_config8(ctrl.d0f3, 0x66, 0x82);
 484
 485         /* DRAM Control */
 486         pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
 487
 488         /* Disable refresh for now */
 489         pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
 490
 491         /* DDR Clock Gen Duty Cycle Control */
 492         pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
 493
 494
 495         /* DRAM Clock Control */
 496         pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
 497
 498         /* DRAM Bus Turn-Around Setting */
 499         pci_write_config8(ctrl.d0f3, 0x60, 0x01);
 500
 501         /* Disable DRAM refresh */
 502         pci_write_config8(ctrl.d0f3,0x6a,0x0);
 503
 504
 505         /* Memory Pads Driving and Range Select */
 506         pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
 507         pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
 508         pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
 509
 510         /* DRAM signal timing control */
 511         pci_write_config8(ctrl.d0f3, 0x74, 0x99);
 512         pci_write_config8(ctrl.d0f3, 0x76, 0x09);
 513         pci_write_config8(ctrl.d0f3, 0x77, 0x12);
 514
 515         pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
 516         pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
 517         pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
 518         pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
 519         pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
 520
 521
 522         /* SPD byte 5  # of physical banks */
 523         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
 524         c = b | 0x40;
 525
 526         pci_write_config8(ctrl.d0f3, 0xb0, c);
 527
 528         /* Set RAM Decode method */
 529         pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
 530
 531         /* Enable DIMM Ranks */
 532         pci_write_config8(ctrl.d0f3, 0x48, ma);
 533         udelay(200);
 534
 535         c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
 536         c &= 0x08;
 537         if ( c == 0x08 )
 538         {
 539                 print_debug("Setting Burst Length 8\n");
 540                 /*
 541                 CPU Frequency  Device 0 Function 2 Offset 54
 542
 543                         CPU FSB Operating Frequency (bits 7:5)
 544                         000 : 100MHz    001 : 133MHz
 545                         010 : 200MHz
 546                                 011->111 : Reserved
 547
 548                         SDRAM BL8 (4)
 549
 550                         Don't change Frequency from power up defaults
 551                         This seems to lockup the RAM interface
 552                 */
 553                 c = pci_read_config8(ctrl.d0f2, 0x54);
 554                 c |= 0x10;
 555                 pci_write_config8(ctrl.d0f2, 0x54, c);
 556                 i = 0x008;              // Used later to set SDRAM MSR
 557         }
 558
 559
 560         for( bank = 0 , bank_address=0; bank <= b ; bank++) {
 561 /*
 562     DDR init described in Via VT8623 BIOS Porting Guide.  Pg 28 (4.2.3.1)
 563 */
 564
 565                 /* NOP command enable */
 566                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 567                 c &= 0xf8;              /* Clear bits 2-0. */
 568                 c |= RAM_COMMAND_NOP;
 569                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 570
 571                 /* read a double word from any address of the dimm */
 572                 dimm_read(bank_address,0x1f000);
 573                 //udelay(200);
 574
 575                 /* All bank precharge Command Enable */
 576                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 577                 c &= 0xf8;              /* Clear bits 2-0. */
 578                 c |= RAM_COMMAND_PRECHARGE;
 579                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 580                 dimm_read(bank_address,0x1f000);
 581
 582
 583                 /* MSR Enable Low DIMM*/
 584                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 585                 c &= 0xf8;              /* Clear bits 2-0. */
 586                 c |= RAM_COMMAND_MSR_LOW;
 587                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 588                 /* TODO: Bank Addressing for Different Numbers of Row Addresses */
 589                 dimm_read(bank_address,0x2000);
 590                 udelay(1);
 591                 dimm_read(bank_address,0x800);
 592                 udelay(1);
 593
 594                 /* All banks precharge Command Enable */
 595                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 596                 c &= 0xf8;              /* Clear bits 2-0. */
 597                 c |= RAM_COMMAND_PRECHARGE;
 598                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 599                 dimm_read(bank_address,0x1f200);
 600
 601                 /* CBR Cycle Enable */
 602                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 603                 c &= 0xf8;              /* Clear bits 2-0. */
 604                 c |= RAM_COMMAND_CBR;
 605                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 606
 607                 /* Read 8 times */
 608                 for (c=0;c<8;c++) {
 609                         dimm_read(bank_address,0x1f300);
 610                         udelay(100);
 611                 }
 612
 613                 /* MSR Enable */
 614                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 615                 c &= 0xf8;              /* Clear bits 2-0. */
 616                 c |= RAM_COMMAND_MSR_LOW;
 617                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 618
 619
 620 /*
 621     Mode Register Definition
 622     with adjustement so that address calculation is correct - 64 bit technology, therefore
 623     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
 624     to DIMM as a row or column address.
 625
 626     MR[9-7]   CAS Latency
 627     MR[6]     Burst Type 0 = sequential, 1 = interleaved
 628     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
 629     MR[0-2]   dont care
 630
 631     CAS Latency
 632     000       reserved
 633     001       reserved
 634     010       2
 635     011       3
 636     100       reserved
 637     101       1.5
 638     110       2.5
 639     111       reserved
 640
 641     CAS 2     0101011000 = 0x158
 642     CAS 2.5   1101011000 = 0x358
 643     CAS 3     0111011000 = 0x1d8
 644
 645 */
 646                 c = pci_read_config8(ctrl.d0f3, 0x56);
 647                 if( (c & 0x30) == 0x10 )
 648                         dimm_read(bank_address,(0x150 + i));
 649                 else if((c & 0x30) == 0x20 )
 650                         dimm_read(bank_address,(0x350 + i));
 651                 else
 652                         dimm_read(bank_address,(0x1d0 + i));
 653
 654
 655                 /* Normal SDRAM Mode */
 656                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 657                 c &= 0xf8;              /* Clear bits 2-0. */
 658                 c |= RAM_COMMAND_NORMAL;
 659                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 660
 661                 bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
 662         } // end of for each bank
 663
 664
 665         /* Set DRAM DQS Output Control */
 666         pci_write_config8(ctrl.d0f3, 0x79, 0x11);
 667
 668         /* Set DQS A/B Input delay to defaults */
 669         pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
 670         pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
 671
 672         /* DQS Duty Cycle Control */
 673         pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 674
 675         /* SPD byte 5  # of physical banks */
 676         b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
 677
 678         /* determine low bond */
 679         if( b == 2)
 680                 bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
 681         else
 682                 bank_address = 0;
 683
 684         for(i = 0x30 ; i < 0x0ff; i++){
 685                 pci_write_config8(ctrl.d0f3,0x70,i);
 686                 // clear
 687                 *(volatile unsigned long*)(0x4000) = 0;
 688                 *(volatile unsigned long*)(0x4100+bank_address) = 0;
 689                 *(volatile unsigned long*)(0x4200) = 0;
 690                 *(volatile unsigned long*)(0x4300+bank_address) = 0;
 691                 *(volatile unsigned long*)(0x4400) = 0;
 692                 *(volatile unsigned long*)(0x4500+bank_address) = 0;
 693
 694                 // fill
 695                 *(volatile unsigned long*)(0x4000) = 0x12345678;
 696                 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
 697                 *(volatile unsigned long*)(0x4200) = 0x78123456;
 698                 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
 699                 *(volatile unsigned long*)(0x4400) = 0x56781234;
 700                 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
 701
 702                         // verify
 703                 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
 704                         continue;
 705
 706                 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
 707                         continue;
 708
 709                 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
 710                         continue;
 711
 712                 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
 713                         continue;
 714
 715                 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
 716                         continue;
 717
 718                 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
 719                         continue;
 720
 721                 // if everything verified then found low bond
 722                 break;
 723
 724         }
 725         print_val("\nLow Bond ",i);
 726         if( i < 0xff ){
 727                 c = i++;
 728                 for(  ; i <0xff ; i++){
 729                         pci_write_config8(ctrl.d0f3,0x70, i);
 730                         // clear
 731                         *(volatile unsigned long*)(0x8000) = 0;
 732                         *(volatile unsigned long*)(0x8100+bank_address) = 0;
 733                         *(volatile unsigned long*)(0x8200) = 0x0;
 734                         *(volatile unsigned long*)(0x8300+bank_address) = 0;
 735                         *(volatile unsigned long*)(0x8400) = 0x0;
 736                         *(volatile unsigned long*)(0x8500+bank_address) = 0;
 737
 738                         // fill
 739                         *(volatile unsigned long*)(0x8000) = 0x12345678;
 740                         *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
 741                         *(volatile unsigned long*)(0x8200) = 0x78123456;
 742                         *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
 743                         *(volatile unsigned long*)(0x8400) = 0x56781234;
 744                         *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
 745
 746                         // verify
 747                         if( *(volatile unsigned long*)(0x8000) != 0x12345678)
 748                                 break;
 749
 750                         if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
 751                                 break;
 752
 753                         if( *(volatile unsigned long*)(0x8200) != 0x78123456)
 754                                 break;
 755
 756                         if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
 757                                 break;
 758
 759                         if( *(volatile unsigned long*)(0x8400) != 0x56781234)
 760                                 break;
 761
 762                         if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
 763                                 break;
 764
 765                 }
 766                 print_val("  High Bond ",i);
 767                 c = ((i - c)<<1)/3 + c;
 768                 print_val("  Setting DQS delay",c);
 769                 print_debug("\n");
 770                 pci_write_config8(ctrl.d0f3,0x70,c);
 771         }else{
 772                 pci_write_config8(ctrl.d0f3,0x70,0x67);
 773         }
 774
 775         /* Set DQS ChA Data Output Delay to the default */
 776         pci_write_config8(ctrl.d0f3, 0x71, 0x65);
 777
 778         /* Set Ch B DQS Output Delays */
 779         pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
 780         pci_write_config8(ctrl.d0f3, 0x73, 0x29);
 781
 782         pci_write_config8(ctrl.d0f3, 0x78, 0x03);
 783
 784         /* Mystery Value */
 785         pci_write_config8(ctrl.d0f3, 0x67, 0x50);
 786
 787         /* Enable Toggle Limiting */
 788         pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
 789
 790 /*
 791     DRAM refresh rate  Device 0 F3 Offset 6a
 792         TODO :: Fix for different DRAM technologies
 793         other than 512Mb and DRAM Freq
 794     Units of 16 DRAM clock cycles - 1.
 795 */
 796         //c = pci_read_config8(ctrl.d0f3, 0x68);
 797         //c &= 0x07;
 798         //b = smbus_read_byte(0x50, SPD_REFRESH);
 799         //print_val("SPD_REFRESH = ", b);
 800
 801         pci_write_config8(ctrl.d0f3,0x6a,0x65);
 802
 803         /* SMM and APIC decoding, we do not use SMM */
 804         b = 0x29;
 805         pci_write_config8(ctrl.d0f3, 0x86, b);
 806         /* SMM and APIC decoding mirror */
 807         pci_write_config8(ctrl.d0f7, 0xe6, b);
 808
 809         /* Open Up the Rest of the Shadow RAM */
 810         pci_write_config8(ctrl.d0f3,0x80,0xff);
 811         pci_write_config8(ctrl.d0f3,0x81,0xff);
 812
 813         /* pci */
 814         pci_write_config8(ctrl.d0f7,0x70,0x82);
 815         pci_write_config8(ctrl.d0f7,0x73,0x01);
 816         pci_write_config8(ctrl.d0f7,0x76,0x50);
 817
 818         pci_write_config8(ctrl.d0f7,0x71,0xc8);
 819
 820
 821         /* VGA device. */
 822         pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 823         pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
 824     print_debug("CN400 raminit.c done\n");
 825 }