src/northbridge/via/cn400/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
   5  * Copyright (C) 2009 Jon Harrison <bothlyn@blueyonder.co.uk
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 /*
  23   Automatically detect and set up ddr dram on the CN400 chipset.
  24   Assumes DDR400 memory as no attempt is made to clock
  25   the chipset down if slower memory is installed.
  26   So far tested on:
  27         512 Mb DDR400 4 Bank / 2 Rank (1GB) (i.e. double sided)
  28 */
  29 /* ported from Via VT8263 Code*/
  30
  31 #include <spd.h>
  32 #include <delay.h>
  33 #include <cpu/x86/mtrr.h>
  34 #include "cn400.h"
  35
  36 static void dimm_read(unsigned long bank,unsigned long x)
  37 {
  38         //unsigned long eax;
  39         volatile unsigned long y;
  40         //eax =  x;
  41         y = * (volatile unsigned long *) (x+ bank) ;
  42
  43 }
  44
  45
  46 static void print_val(char *str, int val)
  47 {
  48         print_debug(str);
  49         print_debug_hex8(val);
  50 }
  51
  52 /**
  53  * Configure the bus between the CPU and the northbridge. This might be able to
  54  * be moved to post-ram code in the future. For the most part, these registers
  55  * should not be messed around with. These are too complex to explain short of
  56  * copying the datasheets into the comments, but most of these values are from
  57  * the BIOS Porting Guide, so they should work on any board. If they don't,
  58  * try the values from your factory BIOS.
  59  *
  60  * TODO: Changing the DRAM frequency doesn't work (hard lockup).
  61  *
  62  * @param dev The northbridge's CPU Host Interface (D0F2).
  63  */
  64 static void c3_cpu_setup(device_t dev)
  65 {
  66         /* Host bus interface registers (D0F2 0x50-0x67) */
  67         /* Taken from CN700 and updated from running CN400 */
  68         uint8_t reg8;
  69
  70         /* Host Bus I/O Circuit (see datasheet) */
  71         /* Host Address Pullup/down Driving */
  72         pci_write_config8(dev, 0x70, 0x33);
  73         pci_write_config8(dev, 0x71, 0x44);
  74         pci_write_config8(dev, 0x72, 0x33);
  75         pci_write_config8(dev, 0x73, 0x44);
  76
  77         /* Output Delay Stagger Control */
  78         pci_write_config8(dev, 0x74, 0x70);
  79
  80         /* AGTL+ I/O Circuit */
  81         pci_write_config8(dev, 0x75, 0x08);
  82
  83         /* AGTL+ Compensation Status */
  84         pci_write_config8(dev, 0x76, 0x74);
  85
  86         /* AGTL+ Auto Compensation Offest */
  87         pci_write_config8(dev, 0x77, 0x00);
  88         pci_write_config8(dev, 0x78, 0x94);
  89
  90         /* Request phase control */
  91         pci_write_config8(dev, 0x50, 0xA8);
  92
  93         /* Line DRDY# Timing Control */
  94         pci_write_config8(dev, 0x60, 0x00);
  95         pci_write_config8(dev, 0x61, 0x00);
  96         pci_write_config8(dev, 0x62, 0x00);
  97
  98         /* QW DRDY# Timing Control */
  99         pci_write_config8(dev, 0x63, 0x00);
 100         pci_write_config8(dev, 0x64, 0x00);
 101         pci_write_config8(dev, 0x65, 0x00);
 102
 103         /* Read Line Burst DRDY# Timing Control */
 104         pci_write_config8(dev, 0x66, 0x00);
 105         pci_write_config8(dev, 0x67, 0x00);
 106
 107         /* CPU Interface Control */
 108         pci_write_config8(dev, 0x51, 0xFE);
 109         pci_write_config8(dev, 0x52, 0xEF);
 110
 111         /* Arbitration */
 112         pci_write_config8(dev, 0x53, 0x88);
 113
 114         /* Write Policy & Reorder Latecy */
 115         pci_write_config8(dev, 0x56, 0x00);
 116
 117         /* Delivery-Trigger Control */
 118         pci_write_config8(dev, 0x58, 0x00);
 119
 120         /* IPI Control */
 121         pci_write_config8(dev, 0x59, 0x30);
 122
 123         /* CPU Misc Control */
 124         pci_write_config8(dev, 0x5C, 0x00);
 125
 126         /* Write Policy */
 127         pci_write_config8(dev, 0x5d, 0xb2);
 128
 129         /* Bandwidth Timer */
 130         pci_write_config8(dev, 0x5e, 0x88);
 131
 132         /* CPU Miscellaneous Control */
 133         pci_write_config8(dev, 0x5f, 0xc7);
 134
 135         /* CPU Miscellaneous Control */
 136         pci_write_config8(dev, 0x55, 0x28);
 137         pci_write_config8(dev, 0x57, 0x69);
 138
 139         /* CPU Host Bus Final Setup */
 140         reg8 = pci_read_config8(dev, 0x54);
 141         reg8 |= 0x08;
 142         pci_write_config8(dev, 0x54, reg8);
 143
 144 }
 145
 146 static void ddr_ram_setup(void)
 147 {
 148         uint8_t b, c, bank, ma;
 149         uint16_t i;
 150         unsigned long bank_address;
 151
 152
 153         print_debug("CN400 RAM init starting\n");
 154
 155         pci_write_config8(ctrl.d0f7, 0x75, 0x08);
 156
 157
 158         /* No  Interleaving or Multi Page */
 159         pci_write_config8(ctrl.d0f3, 0x69, 0x00);
 160         pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
 161
 162 /*
 163     DRAM MA Map Type  Device 0  Fn3 Offset 50-51
 164
 165     Determine memory addressing based on the module's memory technology and
 166     arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
 167
 168     Bank 1/0 MA map type   50[7-5]
 169     Bank 1/0 command rate  50[4]
 170     Bank 3/2 MA map type   50[3-1]
 171     Bank 3/2 command rate  50[0]
 172
 173
 174     Read SPD byte 17, Number of banks on SDRAM device.
 175 */
 176         c = 0;
 177         b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
 178         //print_val("Detecting Memory\nNumber of Banks ",b);
 179
 180         // Only supporting 4 bank chips just now
 181         if( b == 4 ){
 182                 /* Read SPD byte 3, Number of row addresses. */
 183                 c = 0x01;
 184                 bank = 0x40;
 185                 b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
 186                 //print_val("\nNumber of Rows ", b);
 187
 188                 if( b >= 0x0d ){        // 256/512Mb
 189
 190                         if (b == 0x0e)
 191                                 bank = 0x48;
 192                         else
 193                                 bank = 0x44;
 194
 195                         /* Read SPD byte 13, Primary DRAM width. */
 196                         b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
 197                         //print_val("\nPrimary DRAM width", b);
 198                         if( b != 4 )   // not 64/128Mb (x4)
 199                                 c = 0x81;  // 256Mb
 200                 }
 201
 202                 /* Read SPD byte 4, Number of column addresses. */
 203                 b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
 204                 //print_val("\nNo Columns ",b);
 205                 if( b == 10 || b == 11 || b == 12) c |= 0x60;   // 10/11 bit col addr
 206                 if( b == 9 ) c |= 0x40;           // 9 bit col addr
 207                 if( b == 8 ) c |= 0x20;           // 8 bit col addr
 208
 209                 //print_val("\nMA type ", c);
 210                 pci_write_config8(ctrl.d0f3, 0x50, c);
 211
 212         }
 213
 214         /* Disable Upper Banks */
 215         pci_write_config8(ctrl.d0f3, 0x51, 0x00);
 216
 217 /*      else
 218         {
 219                 die("DRAM module size is not supported by CN400\n");
 220         }
 221 */
 222
 223 /*
 224     DRAM bank size.  See 4.3.1 pg 35
 225
 226     5a->5d  set to end address for each bank.  1 bit == 32MB
 227     5a = bank 0
 228     5b = bank 0 + b1
 229     5c = bank 0 + b1 + b2
 230     5d = bank 0 + b1 + b2 + b3
 231 */
 232
 233         // Read SPD byte 31 Module bank density
 234         //c = 0;
 235         b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
 236         if( b & 0x02 )
 237         {
 238                 c = 0x40;                                       // 2GB
 239                 bank |= 0x02;
 240         }
 241         else if( b & 0x01)
 242         {
 243                 c = 0x20;                                       // 1GB
 244                 if (bank == 0x48) bank |= 0x01;
 245                 else bank |= 0x03;
 246         }
 247         else if( b & 0x80)
 248         {
 249                 c = 0x10;                                       // 512MB
 250                 if (bank == 0x44) bank |= 0x02;
 251         }
 252         else if( b & 0x40)
 253         {
 254                 c = 0x08;                                       // 256MB
 255                 if (bank == 0x44) bank |= 0x01;
 256                 else bank |= 0x03;
 257         }
 258         else if( b & 0x20)
 259         {
 260                 c = 0x04;                                       // 128MB
 261                 if (bank == 0x40) bank |= 0x02;
 262         }
 263         else if( b & 0x10)
 264         {
 265                 c = 0x02;                                       // 64MB
 266                 bank |= 0x01;
 267         }
 268         else if( b & 0x08) c = 0x01;            // 32MB
 269         else c = 0x01;                          // Error, use default
 270
 271         // set bank zero size
 272         pci_write_config8(ctrl.d0f3, 0x40, c);
 273
 274         // SPD byte 5  # of physical banks
 275         b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
 276
 277         //print_val("\nNo Physical Banks ",b);
 278         if( b == 2)
 279         {
 280                 c <<=1;
 281                 bank |= 0x80;
 282         }
 283 /*      else
 284         {
 285                 die("Only a single DIMM is supported by EPIA-N(L)\n");
 286         }
 287 */
 288         // set banks 1,2,3...
 289         pci_write_config8(ctrl.d0f3, 0x41,c);
 290         pci_write_config8(ctrl.d0f3, 0x42,c);
 291         pci_write_config8(ctrl.d0f3, 0x43,c);
 292         pci_write_config8(ctrl.d0f3, 0x44,c);
 293         pci_write_config8(ctrl.d0f3, 0x45,c);
 294         pci_write_config8(ctrl.d0f3, 0x46,c);
 295         pci_write_config8(ctrl.d0f3, 0x47,c);
 296
 297         /* Top Rank Address Mirrored to the South Bridge */
 298         /* over the VLink                                                                */
 299         pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
 300
 301         ma = bank;
 302
 303         /* Read SPD byte 18 CAS Latency */
 304         b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
 305 /*      print_debug("\nCAS Supported ");
 306         if(b & 0x04)
 307                 print_debug("2 ");
 308         if(b & 0x08)
 309                 print_debug("2.5 ");
 310         if(b & 0x10)
 311                 print_debug("3");
 312
 313         c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 314         print_val("\nCycle time at CL X     (nS)", c);
 315         c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
 316         print_val("\nCycle time at CL X-0.5 (nS)", c);
 317         c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
 318         print_val("\nCycle time at CL X-1   (nS)", c);
 319 */
 320         /* Scaling of Cycle Time SPD data */
 321         /* 7      4 3       0             */
 322         /*    ns     x0.1ns               */
 323         bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 324
 325         if( b & 0x10 ){             // DDR offering optional CAS 3
 326                 //print_debug("\nStarting at CAS 3");
 327                 c = 0x30;
 328                 /* see if we can better it */
 329                 if( b & 0x08 ){     // DDR mandatory CAS 2.5
 330                         if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
 331                                 //print_debug("\nWe can do CAS 2.5");
 332                                 c = 0x20;
 333                         }
 334                 }
 335                 if( b & 0x04 ){     // DDR mandatory CAS 2
 336                         if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
 337                                 //print_debug("\nWe can do CAS 2");
 338                                 c = 0x10;
 339                         }
 340                 }
 341         }else{                     // no optional CAS values just 2 & 2.5
 342                 //print_debug("\nStarting at CAS 2.5");
 343                 c = 0x20;          // assume CAS 2.5
 344                 if( b & 0x04){      // Should always happen
 345                         if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
 346                                 //print_debug("\nWe can do CAS 2");
 347                                 c = 0x10;
 348                         }
 349                 }
 350         }
 351
 352         /* Scale DRAM Cycle Time to tRP/tRCD */
 353         /* 7      2 1       0             */
 354         /*    ns     x0.25ns               */
 355         if ( bank <= 0x50 ) bank = 0x14;
 356         else if (bank <= 0x60) bank = 0x18;
 357         else bank = 0x1E;
 358
 359 /*
 360     DRAM Timing  Device 0  Fn 3 Offset 56
 361
 362     RAS Pulse width 56[7,6]
 363     CAS Latency     56[5,4]
 364     Row pre-charge  56[1,0]
 365
 366          SDR  DDR
 367       00  1T   -
 368       01  2T   2T
 369       10  3T   2.5T
 370       11  -    3T
 371
 372     RAS/CAS delay   56[3,2]
 373
 374     Determine row pre-charge time (tRP)
 375
 376
 377     Read SPD byte 27, min row pre-charge time.
 378 */
 379
 380         b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
 381
 382         //print_val("\ntRP ",b);
 383         if ( b >= (5 * bank)) {
 384                 c |= 0x03;              // set tRP = 5T
 385         }
 386         else if ( b >= (4 * bank)) {
 387                 c |= 0x02;              // set tRP = 4T
 388         }
 389         else if ( b >= (3 * bank)) {
 390                 c |= 0x01;              // set tRP = 3T
 391         }
 392
 393 /*
 394     Determine RAS to CAS delay (tRCD)
 395
 396     Read SPD byte 29, min row pre-charge time.
 397 */
 398
 399         b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
 400         //print_val("\ntRCD ",b);
 401
 402         if ( b >= (5 * bank)) c |= 0x0C;                // set tRCD = 5T
 403         else if ( b >= (4 * bank)) c |= 0x08;   // set tRCD = 4T
 404         else if ( b >= (3 * bank)) c |= 0x04;   // set tRCD = 3T
 405
 406 /*
 407     Determine RAS pulse width (tRAS)
 408
 409
 410     Read SPD byte 30, device min active to pre-charge time.
 411 */
 412
 413         /* tRAS is in whole ns */
 414         bank = bank >> 2;
 415
 416         b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 417         //print_val("\ntRAS ",b);
 418         //print_val("\nBank ", bank);
 419         if ( b >= (9 * bank)) c |= 0xC0;                // set tRAS = 9T
 420         else if ( b >= (8 * bank)) c |= 0x80;   // set tRAS = 8T
 421         else if ( b >= (7 * bank)) c |= 0x40;   // set tRAS = 7T
 422
 423         /* Write DRAM Timing All Banks I */
 424         pci_write_config8(ctrl.d0f3, 0x56, c);
 425
 426         /* TWrite DRAM Timing All Banks II */
 427         pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
 428
 429         /* DRAM arbitration timer */
 430         pci_write_config8(ctrl.d0f3, 0x65, 0x99);
 431
 432 /*
 433     DRAM Clock  Device 0 Fn 3 Offset 68
 434 */
 435         bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 436
 437         /* Setup DRAM Cycle Time */
 438         if ( bank <= 0x50 )
 439         {
 440                 /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
 441                 /* This sets to 133MHz FSB / DDR400. */
 442                 pci_write_config8(ctrl.d0f3, 0x68, 0x85);
 443         }
 444         else if (bank <= 0x60)
 445         {
 446                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 447                 /* 133MHz FSB / DDR333.  See also c3_cpu_setup */
 448                 pci_write_config8(ctrl.d0f3, 0x68, 0x81);
 449         }
 450         else
 451         {
 452                 /* DRAM DDR Control Alert! Alert! This hardwires to */
 453                 /* 133MHz FSB / DDR266.  See also c3_cpu_setup */
 454                 pci_write_config8(ctrl.d0f3, 0x68, 0x80);
 455         }
 456
 457         /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
 458         udelay(200);
 459
 460 /*
 461     Determine bank interleave
 462
 463     Read SPD byte 17, Number of banks on SDRAM device.
 464 */
 465         c = 0x0F;
 466         b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
 467         if( b == 4) c |= 0x80;
 468         else if (b == 2) c |= 0x40;
 469
 470         /* 4-Way Interleave With Multi-Paging (From Running System)*/
 471         pci_write_config8(ctrl.d0f3, 0x69, c);
 472
 473         /*DRAM Controller Internal Options */
 474         pci_write_config8(ctrl.d0f3, 0x54, 0x01);
 475
 476         /* DRAM Arbitration Control */
 477         pci_write_config8(ctrl.d0f3, 0x66, 0x82);
 478
 479         /* DRAM Control */
 480         pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
 481
 482         /* Disable refresh for now */
 483         pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
 484
 485         /* DDR Clock Gen Duty Cycle Control */
 486         pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
 487
 488
 489         /* DRAM Clock Control */
 490         pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
 491
 492         /* DRAM Bus Turn-Around Setting */
 493         pci_write_config8(ctrl.d0f3, 0x60, 0x01);
 494
 495         /* Disable DRAM refresh */
 496         pci_write_config8(ctrl.d0f3,0x6a,0x0);
 497
 498
 499         /* Memory Pads Driving and Range Select */
 500         pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
 501         pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
 502         pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
 503
 504         /* DRAM signal timing control */
 505         pci_write_config8(ctrl.d0f3, 0x74, 0x99);
 506         pci_write_config8(ctrl.d0f3, 0x76, 0x09);
 507         pci_write_config8(ctrl.d0f3, 0x77, 0x12);
 508
 509         pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
 510         pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
 511         pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
 512         pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
 513         pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
 514
 515
 516         /* SPD byte 5  # of physical banks */
 517         b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
 518         c = b | 0x40;
 519
 520         pci_write_config8(ctrl.d0f3, 0xb0, c);
 521
 522         /* Set RAM Decode method */
 523         pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
 524
 525         /* Enable DIMM Ranks */
 526         pci_write_config8(ctrl.d0f3, 0x48, ma);
 527         udelay(200);
 528
 529         c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
 530         c &= 0x08;
 531         if ( c == 0x08 )
 532         {
 533                 print_debug("Setting Burst Length 8\n");
 534                 /*
 535                 CPU Frequency  Device 0 Function 2 Offset 54
 536
 537                         CPU FSB Operating Frequency (bits 7:5)
 538                         000 : 100MHz    001 : 133MHz
 539                         010 : 200MHz
 540                                 011->111 : Reserved
 541
 542                         SDRAM BL8 (4)
 543
 544                         Don't change Frequency from power up defaults
 545                         This seems to lockup the RAM interface
 546                 */
 547                 c = pci_read_config8(ctrl.d0f2, 0x54);
 548                 c |= 0x10;
 549                 pci_write_config8(ctrl.d0f2, 0x54, c);
 550                 i = 0x008;              // Used later to set SDRAM MSR
 551         }
 552
 553
 554         for( bank = 0 , bank_address=0; bank <= b ; bank++) {
 555 /*
 556     DDR init described in Via VT8623 BIOS Porting Guide.  Pg 28 (4.2.3.1)
 557 */
 558
 559                 /* NOP command enable */
 560                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 561                 c &= 0xf8;              /* Clear bits 2-0. */
 562                 c |= RAM_COMMAND_NOP;
 563                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 564
 565                 /* read a double word from any address of the dimm */
 566                 dimm_read(bank_address,0x1f000);
 567                 //udelay(200);
 568
 569                 /* All bank precharge Command Enable */
 570                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 571                 c &= 0xf8;              /* Clear bits 2-0. */
 572                 c |= RAM_COMMAND_PRECHARGE;
 573                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 574                 dimm_read(bank_address,0x1f000);
 575
 576
 577                 /* MSR Enable Low DIMM*/
 578                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 579                 c &= 0xf8;              /* Clear bits 2-0. */
 580                 c |= RAM_COMMAND_MSR_LOW;
 581                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 582                 /* TODO: Bank Addressing for Different Numbers of Row Addresses */
 583                 dimm_read(bank_address,0x2000);
 584                 udelay(1);
 585                 dimm_read(bank_address,0x800);
 586                 udelay(1);
 587
 588                 /* All banks precharge Command Enable */
 589                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 590                 c &= 0xf8;              /* Clear bits 2-0. */
 591                 c |= RAM_COMMAND_PRECHARGE;
 592                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 593                 dimm_read(bank_address,0x1f200);
 594
 595                 /* CBR Cycle Enable */
 596                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 597                 c &= 0xf8;              /* Clear bits 2-0. */
 598                 c |= RAM_COMMAND_CBR;
 599                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 600
 601                 /* Read 8 times */
 602                 for (c=0;c<8;c++) {
 603                         dimm_read(bank_address,0x1f300);
 604                         udelay(100);
 605                 }
 606
 607                 /* MSR Enable */
 608                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 609                 c &= 0xf8;              /* Clear bits 2-0. */
 610                 c |= RAM_COMMAND_MSR_LOW;
 611                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 612
 613
 614 /*
 615     Mode Register Definition
 616     with adjustement so that address calculation is correct - 64 bit technology, therefore
 617     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
 618     to DIMM as a row or column address.
 619
 620     MR[9-7]   CAS Latency
 621     MR[6]     Burst Type 0 = sequential, 1 = interleaved
 622     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
 623     MR[0-2]   dont care
 624
 625     CAS Latency
 626     000       reserved
 627     001       reserved
 628     010       2
 629     011       3
 630     100       reserved
 631     101       1.5
 632     110       2.5
 633     111       reserved
 634
 635     CAS 2     0101011000 = 0x158
 636     CAS 2.5   1101011000 = 0x358
 637     CAS 3     0111011000 = 0x1d8
 638
 639 */
 640                 c = pci_read_config8(ctrl.d0f3, 0x56);
 641                 if( (c & 0x30) == 0x10 )
 642                         dimm_read(bank_address,(0x150 + i));
 643                 else if((c & 0x30) == 0x20 )
 644                         dimm_read(bank_address,(0x350 + i));
 645                 else
 646                         dimm_read(bank_address,(0x1d0 + i));
 647
 648
 649                 /* Normal SDRAM Mode */
 650                 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
 651                 c &= 0xf8;              /* Clear bits 2-0. */
 652                 c |= RAM_COMMAND_NORMAL;
 653                 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
 654
 655                 bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
 656         } // end of for each bank
 657
 658
 659         /* Set DRAM DQS Output Control */
 660         pci_write_config8(ctrl.d0f3, 0x79, 0x11);
 661
 662         /* Set DQS A/B Input delay to defaults */
 663         pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
 664         pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
 665
 666         /* DQS Duty Cycle Control */
 667         pci_write_config8(ctrl.d0f3, 0xED, 0x11);
 668
 669         /* SPD byte 5  # of physical banks */
 670         b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
 671
 672         /* determine low bond */
 673         if( b == 2)
 674                 bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
 675         else
 676                 bank_address = 0;
 677
 678         for(i = 0x30 ; i < 0x0ff; i++){
 679                 pci_write_config8(ctrl.d0f3,0x70,i);
 680                 // clear
 681                 *(volatile unsigned long*)(0x4000) = 0;
 682                 *(volatile unsigned long*)(0x4100+bank_address) = 0;
 683                 *(volatile unsigned long*)(0x4200) = 0;
 684                 *(volatile unsigned long*)(0x4300+bank_address) = 0;
 685                 *(volatile unsigned long*)(0x4400) = 0;
 686                 *(volatile unsigned long*)(0x4500+bank_address) = 0;
 687
 688                 // fill
 689                 *(volatile unsigned long*)(0x4000) = 0x12345678;
 690                 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
 691                 *(volatile unsigned long*)(0x4200) = 0x78123456;
 692                 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
 693                 *(volatile unsigned long*)(0x4400) = 0x56781234;
 694                 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
 695
 696                         // verify
 697                 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
 698                         continue;
 699
 700                 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
 701                         continue;
 702
 703                 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
 704                         continue;
 705
 706                 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
 707                         continue;
 708
 709                 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
 710                         continue;
 711
 712                 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
 713                         continue;
 714
 715                 // if everything verified then found low bond
 716                 break;
 717
 718         }
 719         print_val("\nLow Bond ",i);
 720         if( i < 0xff ){
 721                 c = i++;
 722                 for(  ; i <0xff ; i++){
 723                         pci_write_config8(ctrl.d0f3,0x70, i);
 724                         // clear
 725                         *(volatile unsigned long*)(0x8000) = 0;
 726                         *(volatile unsigned long*)(0x8100+bank_address) = 0;
 727                         *(volatile unsigned long*)(0x8200) = 0x0;
 728                         *(volatile unsigned long*)(0x8300+bank_address) = 0;
 729                         *(volatile unsigned long*)(0x8400) = 0x0;
 730                         *(volatile unsigned long*)(0x8500+bank_address) = 0;
 731
 732                         // fill
 733                         *(volatile unsigned long*)(0x8000) = 0x12345678;
 734                         *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
 735                         *(volatile unsigned long*)(0x8200) = 0x78123456;
 736                         *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
 737                         *(volatile unsigned long*)(0x8400) = 0x56781234;
 738                         *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
 739
 740                         // verify
 741                         if( *(volatile unsigned long*)(0x8000) != 0x12345678)
 742                                 break;
 743
 744                         if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
 745                                 break;
 746
 747                         if( *(volatile unsigned long*)(0x8200) != 0x78123456)
 748                                 break;
 749
 750                         if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
 751                                 break;
 752
 753                         if( *(volatile unsigned long*)(0x8400) != 0x56781234)
 754                                 break;
 755
 756                         if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
 757                                 break;
 758
 759                 }
 760                 print_val("  High Bond ",i);
 761                 c = ((i - c)<<1)/3 + c;
 762                 print_val("  Setting DQS delay",c);
 763                 print_debug("\n");
 764                 pci_write_config8(ctrl.d0f3,0x70,c);
 765         }else{
 766                 pci_write_config8(ctrl.d0f3,0x70,0x67);
 767         }
 768
 769         /* Set DQS ChA Data Output Delay to the default */
 770         pci_write_config8(ctrl.d0f3, 0x71, 0x65);
 771
 772         /* Set Ch B DQS Output Delays */
 773         pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
 774         pci_write_config8(ctrl.d0f3, 0x73, 0x29);
 775
 776         pci_write_config8(ctrl.d0f3, 0x78, 0x03);
 777
 778         /* Mystery Value */
 779         pci_write_config8(ctrl.d0f3, 0x67, 0x50);
 780
 781         /* Enable Toggle Limiting */
 782         pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
 783
 784 /*
 785     DRAM refresh rate  Device 0 F3 Offset 6a
 786         TODO :: Fix for different DRAM technologies
 787         other than 512Mb and DRAM Freq
 788     Units of 16 DRAM clock cycles - 1.
 789 */
 790         //c = pci_read_config8(ctrl.d0f3, 0x68);
 791         //c &= 0x07;
 792         //b = smbus_read_byte(DIMM0, SPD_REFRESH);
 793         //print_val("SPD_REFRESH = ", b);
 794
 795         pci_write_config8(ctrl.d0f3,0x6a,0x65);
 796
 797         /* SMM and APIC decoding, we do not use SMM */
 798         b = 0x29;
 799         pci_write_config8(ctrl.d0f3, 0x86, b);
 800         /* SMM and APIC decoding mirror */
 801         pci_write_config8(ctrl.d0f7, 0xe6, b);
 802
 803         /* Open Up the Rest of the Shadow RAM */
 804         pci_write_config8(ctrl.d0f3,0x80,0xff);
 805         pci_write_config8(ctrl.d0f3,0x81,0xff);
 806
 807         /* pci */
 808         pci_write_config8(ctrl.d0f7,0x70,0x82);
 809         pci_write_config8(ctrl.d0f7,0x73,0x01);
 810         pci_write_config8(ctrl.d0f7,0x76,0x50);
 811
 812         pci_write_config8(ctrl.d0f7,0x71,0xc8);
 813
 814
 815         /* VGA device. */
 816         pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
 817         pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
 818     print_debug("CN400 raminit.c done\n");
 819 }